Home
last modified time | relevance | path

Searched refs:FPSCR (Results 1 – 10 of 10) sorted by relevance

/OK3568_Linux_fs/kernel/arch/sh/math-emu/
H A Dmath.c27 #define FPSCR (fregs->fpscr) macro
28 #define FPSCR_RM (FPSCR&3)
29 #define FPSCR_DN ((FPSCR>>18)&1)
30 #define FPSCR_PR ((FPSCR>>19)&1)
31 #define FPSCR_SZ ((FPSCR>>20)&1)
32 #define FPSCR_FR ((FPSCR>>21)&1)
341 FPSCR ^= flag; in fxchg()
434 unsigned long *reg = (code & 0x0010) ? &FPUL : &FPSCR; in id_sys()
/OK3568_Linux_fs/kernel/arch/arm/vfp/
H A Dvfphw.S110 VFPFMRX r5, FPSCR @ current status
120 stmia r4, {r1, r5, r6, r8} @ save FPEXC, FPSCR, FPINST, FPINST2
H A Dvfpmodule.c234 fmrx(FPEXC), fmrx(FPSCR), inst); in vfp_panic()
265 fmxr(FPSCR, fpscr); in vfp_raise_exceptions()
345 orig_fpscr = fpscr = fmrx(FPSCR); in VFP_bounce()
/OK3568_Linux_fs/kernel/arch/arm/include/asm/
H A Dvfp.h14 #define FPSCR cr1 macro
/OK3568_Linux_fs/yocto/poky/meta/recipes-devtools/qemu/qemu/
H A D0015-target-ppc-ppc_store_fpscr-doesn-t-update-bits-0-to-.patch61 +/* FPSCR bits that can be set by mtfsf, mtfsfi and mtfsb1 */
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/lib/gcc/arm-none-linux-gnueabihf/10.3.1/plugin/include/config/arm/
H A Darm.h1263 DEF_FP_SYSREG (FPSCR) \
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/arm/gcc-arm-10.3-2021.07-x86_64-arm-none-linux-gnueabihf/share/info/
H A Dgcc.info46671 return the value of the FPSCR register. Note, ISA 3.0 supports the
46677 instruction to write new values to selected fields of the FPSCR. The
46681 32. Hence these instructions only modify the FPSCR[32:63] bits by
46687 FPSCR, masks the current rounding mode bits out and OR's in the new
46741 Otherwise the builtin reads the FPSCR, masks the current decimal rounding
46974 FPSCR. The instruction is a lower latency version of the 'mffs'
46976 builtin uses the older 'mffs' instruction to read the FPSCR.
50683 Returns the value that is currently set in the 'FPSCR' register.
50686 Sets the 'FPSCR' register to the specified value VAL, while
H A Dgccint.info40755 precision operation, the FPSCR PR bit has to be cleared, while for
40758 hence these FPSCR sets have to be inserted before reload, i.e. you
/OK3568_Linux_fs/prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/share/info/
H A Dgcc.info46671 return the value of the FPSCR register. Note, ISA 3.0 supports the
46677 instruction to write new values to selected fields of the FPSCR. The
46681 32. Hence these instructions only modify the FPSCR[32:63] bits by
46687 FPSCR, masks the current rounding mode bits out and OR's in the new
46741 Otherwise the builtin reads the FPSCR, masks the current decimal rounding
46974 FPSCR. The instruction is a lower latency version of the 'mffs'
46976 builtin uses the older 'mffs' instruction to read the FPSCR.
50683 Returns the value that is currently set in the 'FPSCR' register.
50686 Sets the 'FPSCR' register to the specified value VAL, while
H A Dgccint.info40755 precision operation, the FPSCR PR bit has to be cleared, while for
40758 hence these FPSCR sets have to be inserted before reload, i.e. you