1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * arch/arm/include/asm/vfp.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * VFP register definitions. 6*4882a593Smuzhiyun * First, the standard VFP set. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __ASM_VFP_H 10*4882a593Smuzhiyun #define __ASM_VFP_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef CONFIG_AS_VFP_VMRS_FPINST 13*4882a593Smuzhiyun #define FPSID cr0 14*4882a593Smuzhiyun #define FPSCR cr1 15*4882a593Smuzhiyun #define MVFR1 cr6 16*4882a593Smuzhiyun #define MVFR0 cr7 17*4882a593Smuzhiyun #define FPEXC cr8 18*4882a593Smuzhiyun #define FPINST cr9 19*4882a593Smuzhiyun #define FPINST2 cr10 20*4882a593Smuzhiyun #endif 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* FPSID bits */ 23*4882a593Smuzhiyun #define FPSID_IMPLEMENTER_BIT (24) 24*4882a593Smuzhiyun #define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT) 25*4882a593Smuzhiyun #define FPSID_SOFTWARE (1<<23) 26*4882a593Smuzhiyun #define FPSID_FORMAT_BIT (21) 27*4882a593Smuzhiyun #define FPSID_FORMAT_MASK (0x3 << FPSID_FORMAT_BIT) 28*4882a593Smuzhiyun #define FPSID_NODOUBLE (1<<20) 29*4882a593Smuzhiyun #define FPSID_ARCH_BIT (16) 30*4882a593Smuzhiyun #define FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) 31*4882a593Smuzhiyun #define FPSID_CPUID_ARCH_MASK (0x7F << FPSID_ARCH_BIT) 32*4882a593Smuzhiyun #define FPSID_PART_BIT (8) 33*4882a593Smuzhiyun #define FPSID_PART_MASK (0xFF << FPSID_PART_BIT) 34*4882a593Smuzhiyun #define FPSID_VARIANT_BIT (4) 35*4882a593Smuzhiyun #define FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) 36*4882a593Smuzhiyun #define FPSID_REV_BIT (0) 37*4882a593Smuzhiyun #define FPSID_REV_MASK (0xF << FPSID_REV_BIT) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* FPEXC bits */ 40*4882a593Smuzhiyun #define FPEXC_EX (1 << 31) 41*4882a593Smuzhiyun #define FPEXC_EN (1 << 30) 42*4882a593Smuzhiyun #define FPEXC_DEX (1 << 29) 43*4882a593Smuzhiyun #define FPEXC_FP2V (1 << 28) 44*4882a593Smuzhiyun #define FPEXC_VV (1 << 27) 45*4882a593Smuzhiyun #define FPEXC_TFV (1 << 26) 46*4882a593Smuzhiyun #define FPEXC_LENGTH_BIT (8) 47*4882a593Smuzhiyun #define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT) 48*4882a593Smuzhiyun #define FPEXC_IDF (1 << 7) 49*4882a593Smuzhiyun #define FPEXC_IXF (1 << 4) 50*4882a593Smuzhiyun #define FPEXC_UFF (1 << 3) 51*4882a593Smuzhiyun #define FPEXC_OFF (1 << 2) 52*4882a593Smuzhiyun #define FPEXC_DZF (1 << 1) 53*4882a593Smuzhiyun #define FPEXC_IOF (1 << 0) 54*4882a593Smuzhiyun #define FPEXC_TRAP_MASK (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* FPSCR bits */ 57*4882a593Smuzhiyun #define FPSCR_DEFAULT_NAN (1<<25) 58*4882a593Smuzhiyun #define FPSCR_FLUSHTOZERO (1<<24) 59*4882a593Smuzhiyun #define FPSCR_ROUND_NEAREST (0<<22) 60*4882a593Smuzhiyun #define FPSCR_ROUND_PLUSINF (1<<22) 61*4882a593Smuzhiyun #define FPSCR_ROUND_MINUSINF (2<<22) 62*4882a593Smuzhiyun #define FPSCR_ROUND_TOZERO (3<<22) 63*4882a593Smuzhiyun #define FPSCR_RMODE_BIT (22) 64*4882a593Smuzhiyun #define FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) 65*4882a593Smuzhiyun #define FPSCR_STRIDE_BIT (20) 66*4882a593Smuzhiyun #define FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) 67*4882a593Smuzhiyun #define FPSCR_LENGTH_BIT (16) 68*4882a593Smuzhiyun #define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) 69*4882a593Smuzhiyun #define FPSCR_IOE (1<<8) 70*4882a593Smuzhiyun #define FPSCR_DZE (1<<9) 71*4882a593Smuzhiyun #define FPSCR_OFE (1<<10) 72*4882a593Smuzhiyun #define FPSCR_UFE (1<<11) 73*4882a593Smuzhiyun #define FPSCR_IXE (1<<12) 74*4882a593Smuzhiyun #define FPSCR_IDE (1<<15) 75*4882a593Smuzhiyun #define FPSCR_IOC (1<<0) 76*4882a593Smuzhiyun #define FPSCR_DZC (1<<1) 77*4882a593Smuzhiyun #define FPSCR_OFC (1<<2) 78*4882a593Smuzhiyun #define FPSCR_UFC (1<<3) 79*4882a593Smuzhiyun #define FPSCR_IXC (1<<4) 80*4882a593Smuzhiyun #define FPSCR_IDC (1<<7) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* MVFR0 bits */ 83*4882a593Smuzhiyun #define MVFR0_A_SIMD_BIT (0) 84*4882a593Smuzhiyun #define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT) 85*4882a593Smuzhiyun #define MVFR0_SP_BIT (4) 86*4882a593Smuzhiyun #define MVFR0_SP_MASK (0xf << MVFR0_SP_BIT) 87*4882a593Smuzhiyun #define MVFR0_DP_BIT (8) 88*4882a593Smuzhiyun #define MVFR0_DP_MASK (0xf << MVFR0_DP_BIT) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* Bit patterns for decoding the packaged operation descriptors */ 91*4882a593Smuzhiyun #define VFPOPDESC_LENGTH_BIT (9) 92*4882a593Smuzhiyun #define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT) 93*4882a593Smuzhiyun #define VFPOPDESC_UNUSED_BIT (24) 94*4882a593Smuzhiyun #define VFPOPDESC_UNUSED_MASK (0xFF << VFPOPDESC_UNUSED_BIT) 95*4882a593Smuzhiyun #define VFPOPDESC_OPDESC_MASK (~(VFPOPDESC_LENGTH_MASK | VFPOPDESC_UNUSED_MASK)) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 98*4882a593Smuzhiyun void vfp_disable(void); 99*4882a593Smuzhiyun #endif 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #endif /* __ASM_VFP_H */ 102