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Searched refs:FPGA_SET_REG (Results 1 – 9 of 9) sorted by relevance

/OK3568_Linux_fs/u-boot/board/gdsys/common/
H A Dmclink.c39 FPGA_SET_REG(k, mc_control, 0x8000); in mclink_probe()
70 FPGA_SET_REG(0, mc_int, int_status); in mclink_send()
73 FPGA_SET_REG(0, mc_tx_address, addr); in mclink_send()
74 FPGA_SET_REG(0, mc_tx_data, data); in mclink_send()
75 FPGA_SET_REG(0, mc_tx_cmd, (slave & 0x03) << 14); in mclink_send()
76 FPGA_SET_REG(0, mc_control, 0x8001); in mclink_send()
104 FPGA_SET_REG(0, mc_tx_address, addr); in mclink_receive()
105 FPGA_SET_REG(0, mc_tx_cmd, in mclink_receive()
107 FPGA_SET_REG(0, mc_control, 0x8001); in mclink_receive()
H A Dcmd_ioloop.c63 FPGA_SET_REG(fpga, ep.rx_tx_status, status); in io_check_status()
68 FPGA_SET_REG(fpga, ep.rx_tx_status, status); in io_check_status()
100 FPGA_SET_REG(fpga, ep.transmit_data, *p++); in io_send()
103 FPGA_SET_REG(fpga, ep.transmit_data, k); in io_send()
105 FPGA_SET_REG(fpga, ep.rx_tx_control, in io_send()
154 FPGA_SET_REG(fpga, ep.transmit_data, buffer[n]); in io_reflect()
156 FPGA_SET_REG(fpga, ep.rx_tx_control, in io_reflect()
186 FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE); in do_ioreflect()
189 FPGA_SET_REG(fpga, ep.device_address, 1); in do_ioreflect()
252 FPGA_SET_REG(fpga, ep.rx_tx_control, CTRL_PROC_RECEIVE_ENABLE); in do_ioloop()
[all …]
H A Dosd.c42 FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
44 FPGA_SET_REG(screen, osd0.fld, val); \
48 FPGA_SET_REG(screen, osd0.fld, val)
127 FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m); in mpc92469ac_set()
249 FPGA_SET_REG(screen - OSD_DH_BASE, in osd_write_videomem()
252 FPGA_SET_REG(screen, videomem0[offset + k], data[k]); in osd_write_videomem()
254 FPGA_SET_REG(screen, videomem0[offset + k], data[k]); in osd_write_videomem()
H A Dihs_mdio.c46 FPGA_SET_REG(info->fpga, mdio.control, in ihs_mdio_read()
64 FPGA_SET_REG(info->fpga, mdio.address_data, value); in ihs_mdio_write()
65 FPGA_SET_REG(info->fpga, mdio.control, in ihs_mdio_write()
/OK3568_Linux_fs/u-boot/board/gdsys/mpc8308/
H A Dstrider.c239 FPGA_SET_REG(k, extended_control, 0x10); /* enable video */ in last_stage_init()
294 FPGA_SET_REG(bus, gpio.set, pin); in fpga_gpio_set()
299 FPGA_SET_REG(bus, gpio.clear, pin); in fpga_gpio_clear()
317 FPGA_SET_REG(bus, control, val | pin); in fpga_control_set()
325 FPGA_SET_REG(bus, control, val & ~pin); in fpga_control_clear()
447 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_active()
449 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); in mii_mdio_active()
458 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_tristate()
468 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_set_mdio()
470 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); in mii_set_mdio()
[all …]
H A Dhrcon.c241 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin); in fpga_gpio_set()
246 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin); in fpga_gpio_clear()
263 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin); in fpga_control_set()
271 FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin); in fpga_control_clear()
392 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_active()
394 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); in mii_mdio_active()
403 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_mdio_tristate()
413 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO); in mii_set_mdio()
415 FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO); in mii_set_mdio()
439 FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC); in mii_set_mdc()
[all …]
H A Dmpc8308.c84 FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN); in board_early_init_r()
/OK3568_Linux_fs/u-boot/drivers/i2c/
H A Dihs_i2c.c21 FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
23 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); \
27 FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val)
/OK3568_Linux_fs/u-boot/include/
H A Dgdsys_fpga.h26 #define FPGA_SET_REG(ix, fld, val) \ macro