1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2014
3*4882a593Smuzhiyun * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <gdsys_fpga.h>
11*4882a593Smuzhiyun #include <miiphy.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "ihs_mdio.h"
14*4882a593Smuzhiyun
ihs_mdio_idle(struct mii_dev * bus)15*4882a593Smuzhiyun static int ihs_mdio_idle(struct mii_dev *bus)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun struct ihs_mdio_info *info = bus->priv;
18*4882a593Smuzhiyun u16 val;
19*4882a593Smuzhiyun unsigned int ctr = 0;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun do {
22*4882a593Smuzhiyun FPGA_GET_REG(info->fpga, mdio.control, &val);
23*4882a593Smuzhiyun udelay(100);
24*4882a593Smuzhiyun if (ctr++ > 10)
25*4882a593Smuzhiyun return -1;
26*4882a593Smuzhiyun } while (!(val & (1 << 12)));
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun return 0;
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
ihs_mdio_reset(struct mii_dev * bus)31*4882a593Smuzhiyun static int ihs_mdio_reset(struct mii_dev *bus)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun ihs_mdio_idle(bus);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun return 0;
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
ihs_mdio_read(struct mii_dev * bus,int addr,int dev_addr,int regnum)38*4882a593Smuzhiyun static int ihs_mdio_read(struct mii_dev *bus, int addr, int dev_addr,
39*4882a593Smuzhiyun int regnum)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun struct ihs_mdio_info *info = bus->priv;
42*4882a593Smuzhiyun u16 val;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun ihs_mdio_idle(bus);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun FPGA_SET_REG(info->fpga, mdio.control,
47*4882a593Smuzhiyun ((addr & 0x1f) << 5) | (regnum & 0x1f) | (2 << 10));
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* wait for rx data available */
50*4882a593Smuzhiyun udelay(100);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun FPGA_GET_REG(info->fpga, mdio.rx_data, &val);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun return val;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
ihs_mdio_write(struct mii_dev * bus,int addr,int dev_addr,int regnum,u16 value)57*4882a593Smuzhiyun static int ihs_mdio_write(struct mii_dev *bus, int addr, int dev_addr,
58*4882a593Smuzhiyun int regnum, u16 value)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun struct ihs_mdio_info *info = bus->priv;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun ihs_mdio_idle(bus);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun FPGA_SET_REG(info->fpga, mdio.address_data, value);
65*4882a593Smuzhiyun FPGA_SET_REG(info->fpga, mdio.control,
66*4882a593Smuzhiyun ((addr & 0x1f) << 5) | (regnum & 0x1f) | (1 << 10));
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
ihs_mdio_init(struct ihs_mdio_info * info)71*4882a593Smuzhiyun int ihs_mdio_init(struct ihs_mdio_info *info)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun struct mii_dev *bus = mdio_alloc();
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun if (!bus) {
76*4882a593Smuzhiyun printf("Failed to allocate FSL MDIO bus\n");
77*4882a593Smuzhiyun return -1;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun bus->read = ihs_mdio_read;
81*4882a593Smuzhiyun bus->write = ihs_mdio_write;
82*4882a593Smuzhiyun bus->reset = ihs_mdio_reset;
83*4882a593Smuzhiyun strcpy(bus->name, info->name);
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun bus->priv = info;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return mdio_register(bus);
88*4882a593Smuzhiyun }
89