1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2012
3*4882a593Smuzhiyun * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <errno.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <gdsys_fpga.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun enum {
15*4882a593Smuzhiyun MCINT_SLAVE_LINK_CHANGED_EV = 1 << 7,
16*4882a593Smuzhiyun MCINT_TX_ERROR_EV = 1 << 9,
17*4882a593Smuzhiyun MCINT_TX_BUFFER_FREE = 1 << 10,
18*4882a593Smuzhiyun MCINT_TX_PACKET_TRANSMITTED_EV = 1 << 11,
19*4882a593Smuzhiyun MCINT_RX_ERROR_EV = 1 << 13,
20*4882a593Smuzhiyun MCINT_RX_CONTENT_AVAILABLE = 1 << 14,
21*4882a593Smuzhiyun MCINT_RX_PACKET_RECEIVED_EV = 1 << 15,
22*4882a593Smuzhiyun };
23*4882a593Smuzhiyun
mclink_probe(void)24*4882a593Smuzhiyun int mclink_probe(void)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun unsigned int k;
27*4882a593Smuzhiyun int slaves = 0;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun for (k = 0; k < CONFIG_SYS_MCLINK_MAX; ++k) {
30*4882a593Smuzhiyun int timeout = 0;
31*4882a593Smuzhiyun unsigned int ctr = 0;
32*4882a593Smuzhiyun u16 mc_status;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun FPGA_GET_REG(k, mc_status, &mc_status);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun if (!(mc_status & (1 << 15)))
37*4882a593Smuzhiyun break;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun FPGA_SET_REG(k, mc_control, 0x8000);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun FPGA_GET_REG(k, mc_status, &mc_status);
42*4882a593Smuzhiyun while (!(mc_status & (1 << 14))) {
43*4882a593Smuzhiyun udelay(100);
44*4882a593Smuzhiyun if (ctr++ > 500) {
45*4882a593Smuzhiyun timeout = 1;
46*4882a593Smuzhiyun break;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun FPGA_GET_REG(k, mc_status, &mc_status);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun if (timeout)
51*4882a593Smuzhiyun break;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun printf("waited %d us for mclink %d to come up\n", ctr * 100, k);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun slaves++;
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun return slaves;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
mclink_send(u8 slave,u16 addr,u16 data)61*4882a593Smuzhiyun int mclink_send(u8 slave, u16 addr, u16 data)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun unsigned int ctr = 0;
64*4882a593Smuzhiyun u16 int_status;
65*4882a593Smuzhiyun u16 rx_cmd_status;
66*4882a593Smuzhiyun u16 rx_cmd;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* reset interrupt status */
69*4882a593Smuzhiyun FPGA_GET_REG(0, mc_int, &int_status);
70*4882a593Smuzhiyun FPGA_SET_REG(0, mc_int, int_status);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* send */
73*4882a593Smuzhiyun FPGA_SET_REG(0, mc_tx_address, addr);
74*4882a593Smuzhiyun FPGA_SET_REG(0, mc_tx_data, data);
75*4882a593Smuzhiyun FPGA_SET_REG(0, mc_tx_cmd, (slave & 0x03) << 14);
76*4882a593Smuzhiyun FPGA_SET_REG(0, mc_control, 0x8001);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* wait for reply */
79*4882a593Smuzhiyun FPGA_GET_REG(0, mc_int, &int_status);
80*4882a593Smuzhiyun while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) {
81*4882a593Smuzhiyun udelay(100);
82*4882a593Smuzhiyun if (ctr++ > 3)
83*4882a593Smuzhiyun return -ETIMEDOUT;
84*4882a593Smuzhiyun FPGA_GET_REG(0, mc_int, &int_status);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status);
88*4882a593Smuzhiyun rx_cmd = (rx_cmd_status >> 12) & 0x03;
89*4882a593Smuzhiyun if (rx_cmd != 0)
90*4882a593Smuzhiyun printf("mclink_send: received cmd %d, expected %d\n", rx_cmd,
91*4882a593Smuzhiyun 0);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun return 0;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
mclink_receive(u8 slave,u16 addr,u16 * data)96*4882a593Smuzhiyun int mclink_receive(u8 slave, u16 addr, u16 *data)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun u16 rx_cmd_status;
99*4882a593Smuzhiyun u16 rx_cmd;
100*4882a593Smuzhiyun u16 int_status;
101*4882a593Smuzhiyun unsigned int ctr = 0;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* send read request */
104*4882a593Smuzhiyun FPGA_SET_REG(0, mc_tx_address, addr);
105*4882a593Smuzhiyun FPGA_SET_REG(0, mc_tx_cmd,
106*4882a593Smuzhiyun ((slave & 0x03) << 14) | (1 << 12) | (1 << 0));
107*4882a593Smuzhiyun FPGA_SET_REG(0, mc_control, 0x8001);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* wait for reply */
111*4882a593Smuzhiyun FPGA_GET_REG(0, mc_int, &int_status);
112*4882a593Smuzhiyun while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) {
113*4882a593Smuzhiyun udelay(100);
114*4882a593Smuzhiyun if (ctr++ > 3)
115*4882a593Smuzhiyun return -ETIMEDOUT;
116*4882a593Smuzhiyun FPGA_GET_REG(0, mc_int, &int_status);
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* check reply */
120*4882a593Smuzhiyun FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status);
121*4882a593Smuzhiyun if ((rx_cmd_status >> 14) != slave) {
122*4882a593Smuzhiyun printf("mclink_receive: reply from slave %d, expected %d\n",
123*4882a593Smuzhiyun rx_cmd_status >> 14, slave);
124*4882a593Smuzhiyun return -EINVAL;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun rx_cmd = (rx_cmd_status >> 12) & 0x03;
128*4882a593Smuzhiyun if (rx_cmd != 1) {
129*4882a593Smuzhiyun printf("mclink_send: received cmd %d, expected %d\n",
130*4882a593Smuzhiyun rx_cmd, 1);
131*4882a593Smuzhiyun return -EIO;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun FPGA_GET_REG(0, mc_rx_data, data);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun return 0;
137*4882a593Smuzhiyun }
138