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Searched refs:FMT_BIT_DEPTH_CONTROL (Results 1 – 13 of 13) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_opp.h45 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
87 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
101 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
102 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\
103 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\
104 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\
105 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\
106 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\
107 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\
108 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\
[all …]
H A Ddce_opp.c111 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation()
120 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation()
126 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation()
136 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation()
158 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation()
165 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation()
170 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation()
179 REG_UPDATE_2(FMT_BIT_DEPTH_CONTROL, in dce60_set_truncation()
206 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
211 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_opp.c55 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in opp1_set_truncation()
66 REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL, in opp1_set_spatial_dither()
123 REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL, in opp1_set_spatial_dither()
H A Ddcn10_opp.h37 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
54 uint32_t FMT_BIT_DEPTH_CONTROL; \
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v10_0.c537 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
538 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
539 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt()
540 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); in dce_v10_0_program_fmt()
542 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt()
543 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); in dce_v10_0_program_fmt()
549 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
550 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
551 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
552 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt()
[all …]
H A Ddce_v11_0.c563 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
564 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
565 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt()
566 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); in dce_v11_0_program_fmt()
568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v11_0_program_fmt()
569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); in dce_v11_0_program_fmt()
575 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
576 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
577 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
578 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt()
[all …]
H A Dsid.h2104 #define FMT_BIT_DEPTH_CONTROL 0x1bf2 macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dcikd.h987 #define FMT_BIT_DEPTH_CONTROL 0x6fc8 macro
H A Devergreend.h1376 #define FMT_BIT_DEPTH_CONTROL 0x6fc8 macro
H A Dr600d.h1245 #define FMT_BIT_DEPTH_CONTROL 0x6710 macro
H A Dr600.c346 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
H A Devergreen.c1348 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt()
H A Dcik.c8801 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_fmt()