Searched refs:DXnGCR0 (Results 1 – 4 of 4) sorted by relevance
218 setbits_le32(DXnGCR0(0), 0x3 << 9); in mctl_channel_init()219 setbits_le32(DXnGCR0(1), 0x3 << 9); in mctl_channel_init()221 clrbits_le32(DXnGCR0(0), 0x3 << 9); in mctl_channel_init()222 clrbits_le32(DXnGCR0(1), 0x3 << 9); in mctl_channel_init()275 writel(0x0, DXnGCR0(1)); /* Disable high DQ */ in mctl_channel_init()
367 writel(0x0, DXnGCR0(1)); /* Disable high DQ */ in mctl_channel_init()
147 #define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x) macro
152 #define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x) macro