Searched refs:DMA_CHAN_TX_CONTROL (Results 1 – 4 of 4) sorted by relevance
96 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_init_tx_chan()102 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_init_tx_chan()171 reg_space[DMA_CHAN_TX_CONTROL(channel) / 4] = in _dwmac4_dump_dma_regs()172 readl(ioaddr + DMA_CHAN_TX_CONTROL(channel)); in _dwmac4_dump_dma_regs()439 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tso()441 ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tso()444 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tso()446 ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tso()491 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tbs()498 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_enable_tbs()[all …]
40 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_start_tx()43 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_start_tx()52 u32 value = readl(ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_stop_tx()55 writel(value, ioaddr + DMA_CHAN_TX_CONTROL(chan)); in dwmac4_dma_stop_tx()
99 #define DMA_CHAN_TX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x4) macro
97 #define DMA_CHAN_TX_CONTROL(x) (DMA_CHANX_BASE_ADDR(x) + 0x4) macro1259 mode = readl(priv->ioaddr + DMA_CHAN_TX_CONTROL(0)); in dwmac_rk_init()1262 writel(mode, priv->ioaddr + DMA_CHAN_TX_CONTROL(0)); in dwmac_rk_init()