Searched refs:DEBUG_WR_REG (Results 1 – 4 of 4) sorted by relevance
| /OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/serdes/axp/ |
| H A D | high_speed_env_lib.c | 317 DEBUG_WR_REG(CPU_AVS_CONTROL0_REG, tmp2); in serdes_phy_config()
335 DEBUG_WR_REG(CORE_AVS_CONTROL_0REG, core_avs); in serdes_phy_config()
341 DEBUG_WR_REG(CORE_AVS_CONTROL_2REG, core_avs); in serdes_phy_config()
348 DEBUG_WR_REG(GENERAL_PURPOSE_RESERVED0_REG, in serdes_phy_config()
353 DEBUG_WR_REG(CPU_AVS_CONTROL2_REG, cpu_avs); in serdes_phy_config()
371 DEBUG_WR_REG(SERDES_LINE_MUX_REG_0_7, 0x11111111); in serdes_phy_config()
375 …DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x002 << 16) | 0xf44d); /* SETM0 - start calibration … in serdes_phy_config()
377 …DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x302 << 16) | 0xf44d); /* SETM1 - start calibration … in serdes_phy_config()
379 …DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x001 << 16) | 0xf801); /* SETM0 - SATA mode & 25MHz ref clk … in serdes_phy_config()
381 …DEBUG_WR_REG(PEX_PHY_ACCESS_REG(1), (0x301 << 16) | 0xf801); /* SETM1 - SATA mode & 25MHz ref clk … in serdes_phy_config()
[all …]
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| /OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_init.h | 34 #define DEBUG_WR_REG(reg, val) \ macro
44 #define DEBUG_WR_REG(reg, val) macro
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/serdes/a38x/ |
| H A D | ctrl_pex.c | 178 DEBUG_WR_REG(PEX_LINK_CTRL_STATUS2_REG(pex_idx), tmp); in hws_pex_config()
184 DEBUG_WR_REG(PEX_CTRL_REG(pex_idx), tmp); in hws_pex_config()
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| /OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_init.h | 49 #define DEBUG_WR_REG(reg, val) \ macro
59 #define DEBUG_WR_REG(reg, val) macro
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