Searched refs:DEBUG_INIT_FULL_S (Results 1 – 8 of 8) sorted by relevance
362 DEBUG_INIT_FULL_S("info->line0_7= 0x"); in serdes_phy_config()364 DEBUG_INIT_FULL_S(" info->line8_15= 0x"); in serdes_phy_config()366 DEBUG_INIT_FULL_S("\n"); in serdes_phy_config()369 DEBUG_INIT_FULL_S("ETM module detect Step 0.9:\n"); in serdes_phy_config()397 DEBUG_INIT_FULL_S("Step 1: First phase of PEX-PIPE Configuration\n"); in serdes_phy_config()431 DEBUG_INIT_FULL_S("Step 2: Configure the desire PIN_PHY_GEN\n"); in serdes_phy_config()498 DEBUG_INIT_FULL_S("Step 3 QSGMII enable\n"); in serdes_phy_config()515 DEBUG_INIT_FULL_S("Step 4: Configure SERDES MUXes\n"); in serdes_phy_config()527 DEBUG_INIT_FULL_S("Step 5: Activate the RX High Impedance Mode\n"); in serdes_phy_config()534 DEBUG_INIT_FULL_S("SERDES "); in serdes_phy_config()[all …]
28 DEBUG_INIT_FULL_S("\n### hws_pex_config ###\n"); in hws_pex_config()84 DEBUG_INIT_FULL_S("Support gen1/gen2\n"); in hws_pex_config()93 DEBUG_INIT_FULL_S(" serdes_type=0x"); in hws_pex_config()95 DEBUG_INIT_FULL_S("\n"); in hws_pex_config()96 DEBUG_INIT_FULL_S(" idx=0x"); in hws_pex_config()98 DEBUG_INIT_FULL_S("\n"); in hws_pex_config()136 DEBUG_INIT_FULL_S in hws_pex_config()143 DEBUG_INIT_FULL_S("PCIe, Idx "); in hws_pex_config()232 DEBUG_INIT_FULL_S("\n### pex_local_bus_num_set ###\n"); in pex_local_bus_num_set()253 DEBUG_INIT_FULL_S("\n### pex_local_dev_num_set ###\n"); in pex_local_dev_num_set()
892 DEBUG_INIT_FULL_S("\n### serdes_seq38x_init ###\n"); in hws_serdes_seq_db_init()1301 DEBUG_INIT_FULL_S("\n### serdes_type_and_speed_to_speed_seq ###\n"); in serdes_type_and_speed_to_speed_seq()1416 DEBUG_INIT_FULL_S("\n### ctrl_high_speed_serdes_phy_config ###\n"); in serdes_phy_config()1429 DEBUG_INIT_FULL_S in serdes_phy_config()1442 DEBUG_INIT_FULL_S in serdes_phy_config()1447 DEBUG_INIT_FULL_S in serdes_phy_config()1486 DEBUG_INIT_FULL_S("\n### hws_power_up_serdes_lanes ###\n"); in hws_power_up_serdes_lanes()1489 DEBUG_INIT_FULL_S in hws_power_up_serdes_lanes()1495 DEBUG_INIT_FULL_S in hws_power_up_serdes_lanes()1498 DEBUG_INIT_FULL_S("\n"); in hws_power_up_serdes_lanes()[all …]
38 DEBUG_INIT_FULL_S("\n### serdes_seq_init ###\n"); in hws_serdes_seq_init()59 DEBUG_INIT_FULL_S("\n### hws_serdes_silicon_ref_clock_get ###\n"); in hws_serdes_silicon_ref_clock_get()
31 #define DEBUG_INIT_FULL_S(s) puts(s) macro41 #define DEBUG_INIT_FULL_S(s) macro49 { DEBUG_INIT_FULL_S(s); DEBUG_INIT_FULL_D(d, l); DEBUG_INIT_FULL_S("\n"); }
720 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - ECC Enabled\n");722 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - ECC Disabled\n");731 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - R-DIMM\n");733 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - U-DIMM\n");743 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 64Bits\n");745 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 32Bits\n");748 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 16Bits\n");754 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 32Bits\n");756 DEBUG_INIT_FULL_S("DDR3 - DUNIT-SET - Datawidth - 16Bits\n");
162 DEBUG_INIT_FULL_S("DDR3 Training Sequence - Switching XBAR Window to FastPath Window\n"); in ddr3_restore_and_set_final_windows()468 DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static MC Init\n"); in ddr3_init_main()598 DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static Training Parameters\n"); in ddr3_init_main()611 DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n"); in ddr3_init_main()628 DEBUG_INIT_FULL_S("DDR3 Training Sequence - HW Training Procedure\n"); in ddr3_init_main()634 DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n"); in ddr3_init_main()
46 #define DEBUG_INIT_FULL_S(s) puts(s) macro56 #define DEBUG_INIT_FULL_S(s) macro64 { DEBUG_INIT_FULL_S(s); \66 DEBUG_INIT_FULL_S("\n"); }