Searched refs:D2H_READY_WD_RESET_COUNT (Results 1 – 9 of 9) sorted by relevance
648 #define D2H_READY_WD_RESET_COUNT (84 * 1000) /* ~84secs >~ BL ready time after wd rst */ macro654 #define D2H_READY_WD_RESET_COUNT (200) /* ~200ms >~ BL ready time after wd rst */ macro
1210 #define D2H_READY_WD_RESET_COUNT (84) /* ~84secs >~ BL ready time after wd rst */ macro1216 #define D2H_READY_WD_RESET_COUNT (200) /* ~200ms >~ BL ready time after wd rst */ macro
647 #define D2H_READY_WD_RESET_COUNT (84 * 1000) /* ~84secs >~ BL ready time after wd rst */ macro653 #define D2H_READY_WD_RESET_COUNT (200) /* ~200ms >~ BL ready time after wd rst */ macro
7866 int print_interval = D2H_READY_WD_RESET_COUNT / 10; in dhdpcie_dongle_host_post_wd_reset_sequence()7875 for (idx = D2H_READY_WD_RESET_COUNT; idx > 0; idx--) { in dhdpcie_dongle_host_post_wd_reset_sequence()7915 int print_interval = D2H_READY_WD_RESET_COUNT / 10; in dhdpcie_dongle_host_pre_chipid_access_sequence()7925 for (idx = D2H_READY_WD_RESET_COUNT; idx > 0; idx--) { in dhdpcie_dongle_host_pre_chipid_access_sequence()
7858 int print_interval = D2H_READY_WD_RESET_COUNT / 10; in dhdpcie_dongle_host_post_wd_reset_sequence()7867 for (idx = D2H_READY_WD_RESET_COUNT; idx > 0; idx--) { in dhdpcie_dongle_host_post_wd_reset_sequence()7907 int print_interval = D2H_READY_WD_RESET_COUNT / 10; in dhdpcie_dongle_host_pre_chipid_access_sequence()7917 for (idx = D2H_READY_WD_RESET_COUNT; idx > 0; idx--) { in dhdpcie_dongle_host_pre_chipid_access_sequence()