1 /* 2 * SDIO spec header file 3 * Protocol and standard (common) device definitions 4 * 5 * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation 6 * 7 * Copyright (C) 1999-2017, Broadcom Corporation 8 * 9 * Unless you and Broadcom execute a separate written software license 10 * agreement governing use of this software, this software is licensed to you 11 * under the terms of the GNU General Public License version 2 (the "GPL"), 12 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 13 * following added to such license: 14 * 15 * As a special exception, the copyright holders of this software give you 16 * permission to link this software with independent modules, and to copy and 17 * distribute the resulting executable under terms of your choice, provided that 18 * you also meet, for each linked independent module, the terms and conditions of 19 * the license of that module. An independent module is a module which is not 20 * derived from this software. The special exception does not apply to any 21 * modifications of the software. 22 * 23 * Notwithstanding the above, under no circumstances may you combine this 24 * software in any way with any other Broadcom software provided under a license 25 * other than the GPL, without Broadcom's express prior written consent. 26 * 27 * 28 * <<Broadcom-WL-IPTag/Open:>> 29 * 30 * $Id: sdio.h 689948 2017-03-14 05:21:03Z $ 31 */ 32 33 #ifndef _SDIO_H 34 #define _SDIO_H 35 36 #ifdef BCMSDIO 37 38 /* CCCR structure for function 0 */ 39 typedef volatile struct { 40 uint8 cccr_sdio_rev; /* RO, cccr and sdio revision */ 41 uint8 sd_rev; /* RO, sd spec revision */ 42 uint8 io_en; /* I/O enable */ 43 uint8 io_rdy; /* I/O ready reg */ 44 uint8 intr_ctl; /* Master and per function interrupt enable control */ 45 uint8 intr_status; /* RO, interrupt pending status */ 46 uint8 io_abort; /* read/write abort or reset all functions */ 47 uint8 bus_inter; /* bus interface control */ 48 uint8 capability; /* RO, card capability */ 49 50 uint8 cis_base_low; /* 0x9 RO, common CIS base address, LSB */ 51 uint8 cis_base_mid; 52 uint8 cis_base_high; /* 0xB RO, common CIS base address, MSB */ 53 54 /* suspend/resume registers */ 55 uint8 bus_suspend; /* 0xC */ 56 uint8 func_select; /* 0xD */ 57 uint8 exec_flag; /* 0xE */ 58 uint8 ready_flag; /* 0xF */ 59 60 uint8 fn0_blk_size[2]; /* 0x10(LSB), 0x11(MSB) */ 61 62 uint8 power_control; /* 0x12 (SDIO version 1.10) */ 63 64 uint8 speed_control; /* 0x13 */ 65 } sdio_regs_t; 66 67 /* SDIO Device CCCR offsets */ 68 #define SDIOD_CCCR_REV 0x00 69 #define SDIOD_CCCR_SDREV 0x01 70 #define SDIOD_CCCR_IOEN 0x02 71 #define SDIOD_CCCR_IORDY 0x03 72 #define SDIOD_CCCR_INTEN 0x04 73 #define SDIOD_CCCR_INTPEND 0x05 74 #define SDIOD_CCCR_IOABORT 0x06 75 #define SDIOD_CCCR_BICTRL 0x07 76 #define SDIOD_CCCR_CAPABLITIES 0x08 77 #define SDIOD_CCCR_CISPTR_0 0x09 78 #define SDIOD_CCCR_CISPTR_1 0x0A 79 #define SDIOD_CCCR_CISPTR_2 0x0B 80 #define SDIOD_CCCR_BUSSUSP 0x0C 81 #define SDIOD_CCCR_FUNCSEL 0x0D 82 #define SDIOD_CCCR_EXECFLAGS 0x0E 83 #define SDIOD_CCCR_RDYFLAGS 0x0F 84 #define SDIOD_CCCR_BLKSIZE_0 0x10 85 #define SDIOD_CCCR_BLKSIZE_1 0x11 86 #define SDIOD_CCCR_POWER_CONTROL 0x12 87 #define SDIOD_CCCR_SPEED_CONTROL 0x13 88 #define SDIOD_CCCR_UHSI_SUPPORT 0x14 89 #define SDIOD_CCCR_DRIVER_STRENGTH 0x15 90 #define SDIOD_CCCR_INTR_EXTN 0x16 91 92 /* Broadcom extensions (corerev >= 1) */ 93 #define SDIOD_CCCR_BRCM_CARDCAP 0xf0 94 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02 95 #define SDIOD_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04 96 #define SDIOD_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08 97 #define SDIOD_CCCR_BRCM_CARDCAP_CHIPID_PRESENT 0x40 98 #define SDIOD_CCCR_BRCM_CARDCAP_SECURE_MODE 0x80 99 100 #define SDIOD_CCCR_BRCM_CARDCTL 0xf1 101 #define SDIOD_CCCR_BRCM_CISLOADED 0x1 102 #define SDIOD_CCCR_BRCM_WLANRST_ONF0ABORT 0x2 103 #define SDIOD_CCCR_BRCM_SDIORST_ONWLANRST 0x20 104 105 #define SDIOD_CCCR_BRCM_SEPINT 0xf2 106 107 /* cccr_sdio_rev */ 108 #define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */ 109 #define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */ 110 #define SDIO_SPEC_VERSION_3_0 0x40 /* SDIO spec version 3.0 */ 111 112 /* sd_rev */ 113 #define SD_REV_PHY_MASK 0x0f /* SD format version number */ 114 115 /* io_en */ 116 #define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */ 117 #define SDIO_FUNC_ENABLE_2 0x04 /* function 2 I/O enable */ 118 #if defined(BT_OVER_SDIO) 119 #define SDIO_FUNC_ENABLE_3 0x08 /* function 2 I/O enable */ 120 #define SDIO_FUNC_DISABLE_3 0xF0 /* function 2 I/O enable */ 121 #endif /* defined (BT_OVER_SDIO) */ 122 123 /* io_rdys */ 124 #define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */ 125 #define SDIO_FUNC_READY_2 0x04 /* function 2 I/O ready */ 126 127 /* intr_ctl */ 128 #define INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */ 129 #define INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */ 130 #define INTR_CTL_FUNC2_EN 0x4 /* interrupt enable for function 2 */ 131 #if defined(BT_OVER_SDIO) 132 #define INTR_CTL_FUNC3_EN 0x8 /* interrupt enable for function 3 */ 133 #endif /* defined (BT_OVER_SDIO) */ 134 /* intr_status */ 135 #define INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */ 136 #define INTR_STATUS_FUNC2 0x4 /* interrupt pending for function 2 */ 137 138 /* io_abort */ 139 #define IO_ABORT_RESET_ALL 0x08 /* I/O card reset */ 140 #define IO_ABORT_FUNC_MASK 0x07 /* abort selction: function x */ 141 142 /* bus_inter */ 143 #define BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */ 144 #define BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */ 145 #define BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */ 146 #define BUS_SD_DATA_WIDTH_MASK 0x03 /* bus width mask */ 147 #define BUS_SD_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */ 148 #define BUS_SD_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */ 149 150 /* capability */ 151 #define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */ 152 #define SDIO_CAP_LSC 0x40 /* low speed card */ 153 #define SDIO_CAP_E4MI 0x20 /* enable interrupt between block of data in 4-bit mode */ 154 #define SDIO_CAP_S4MI 0x10 /* support interrupt between block of data in 4-bit mode */ 155 #define SDIO_CAP_SBS 0x08 /* support suspend/resume */ 156 #define SDIO_CAP_SRW 0x04 /* support read wait */ 157 #define SDIO_CAP_SMB 0x02 /* support multi-block transfer */ 158 #define SDIO_CAP_SDC 0x01 /* Support Direct commands during multi-byte transfer */ 159 160 /* power_control */ 161 #define SDIO_POWER_SMPC 0x01 /* supports master power control (RO) */ 162 #define SDIO_POWER_EMPC 0x02 /* enable master power control (allow > 200mA) (RW) */ 163 164 /* speed_control (control device entry into high-speed clocking mode) */ 165 #define SDIO_SPEED_SHS 0x01 /* supports high-speed [clocking] mode (RO) */ 166 #define SDIO_SPEED_EHS 0x02 /* enable high-speed [clocking] mode (RW) */ 167 #define SDIO_SPEED_UHSI_DDR50 0x08 168 169 /* for setting bus speed in card: 0x13h */ 170 #define SDIO_BUS_SPEED_UHSISEL_M BITFIELD_MASK(3) 171 #define SDIO_BUS_SPEED_UHSISEL_S 1 172 173 /* for getting bus speed cap in card: 0x14h */ 174 #define SDIO_BUS_SPEED_UHSICAP_M BITFIELD_MASK(3) 175 #define SDIO_BUS_SPEED_UHSICAP_S 0 176 177 /* for getting driver type CAP in card: 0x15h */ 178 #define SDIO_BUS_DRVR_TYPE_CAP_M BITFIELD_MASK(3) 179 #define SDIO_BUS_DRVR_TYPE_CAP_S 0 180 181 /* for setting driver type selection in card: 0x15h */ 182 #define SDIO_BUS_DRVR_TYPE_SEL_M BITFIELD_MASK(2) 183 #define SDIO_BUS_DRVR_TYPE_SEL_S 4 184 185 /* for getting async int support in card: 0x16h */ 186 #define SDIO_BUS_ASYNCINT_CAP_M BITFIELD_MASK(1) 187 #define SDIO_BUS_ASYNCINT_CAP_S 0 188 189 /* for setting async int selection in card: 0x16h */ 190 #define SDIO_BUS_ASYNCINT_SEL_M BITFIELD_MASK(1) 191 #define SDIO_BUS_ASYNCINT_SEL_S 1 192 193 /* brcm sepint */ 194 #define SDIO_SEPINT_MASK 0x01 /* route sdpcmdev intr onto separate pad (chip-specific) */ 195 #define SDIO_SEPINT_OE 0x02 /* 1 asserts output enable for above pad */ 196 #define SDIO_SEPINT_ACT_HI 0x04 /* use active high interrupt level instead of active low */ 197 198 /* FBR structure for function 1-7, FBR addresses and register offsets */ 199 typedef volatile struct { 200 uint8 devctr; /* device interface, CSA control */ 201 uint8 ext_dev; /* extended standard I/O device type code */ 202 uint8 pwr_sel; /* power selection support */ 203 uint8 PAD[6]; /* reserved */ 204 205 uint8 cis_low; /* CIS LSB */ 206 uint8 cis_mid; 207 uint8 cis_high; /* CIS MSB */ 208 uint8 csa_low; /* code storage area, LSB */ 209 uint8 csa_mid; 210 uint8 csa_high; /* code storage area, MSB */ 211 uint8 csa_dat_win; /* data access window to function */ 212 213 uint8 fnx_blk_size[2]; /* block size, little endian */ 214 } sdio_fbr_t; 215 216 /* Maximum number of I/O funcs */ 217 #define SDIOD_MAX_FUNCS 8 218 #define SDIOD_MAX_IOFUNCS 7 219 220 /* SDIO Device FBR Start Address */ 221 #define SDIOD_FBR_STARTADDR 0x100 222 223 /* SDIO Device FBR Size */ 224 #define SDIOD_FBR_SIZE 0x100 225 226 /* Macro to calculate FBR register base */ 227 #define SDIOD_FBR_BASE(n) ((n) * 0x100) 228 229 /* Function register offsets */ 230 #define SDIOD_FBR_DEVCTR 0x00 /* basic info for function */ 231 #define SDIOD_FBR_EXT_DEV 0x01 /* extended I/O device code */ 232 #define SDIOD_FBR_PWR_SEL 0x02 /* power selection bits */ 233 234 /* SDIO Function CIS ptr offset */ 235 #define SDIOD_FBR_CISPTR_0 0x09 236 #define SDIOD_FBR_CISPTR_1 0x0A 237 #define SDIOD_FBR_CISPTR_2 0x0B 238 239 /* Code Storage Area pointer */ 240 #define SDIOD_FBR_CSA_ADDR_0 0x0C 241 #define SDIOD_FBR_CSA_ADDR_1 0x0D 242 #define SDIOD_FBR_CSA_ADDR_2 0x0E 243 #define SDIOD_FBR_CSA_DATA 0x0F 244 245 /* SDIO Function I/O Block Size */ 246 #define SDIOD_FBR_BLKSIZE_0 0x10 247 #define SDIOD_FBR_BLKSIZE_1 0x11 248 249 /* devctr */ 250 #define SDIOD_FBR_DEVCTR_DIC 0x0f /* device interface code */ 251 #define SDIOD_FBR_DECVTR_CSA 0x40 /* CSA support flag */ 252 #define SDIOD_FBR_DEVCTR_CSA_EN 0x80 /* CSA enabled */ 253 /* interface codes */ 254 #define SDIOD_DIC_NONE 0 /* SDIO standard interface is not supported */ 255 #define SDIOD_DIC_UART 1 256 #define SDIOD_DIC_BLUETOOTH_A 2 257 #define SDIOD_DIC_BLUETOOTH_B 3 258 #define SDIOD_DIC_GPS 4 259 #define SDIOD_DIC_CAMERA 5 260 #define SDIOD_DIC_PHS 6 261 #define SDIOD_DIC_WLAN 7 262 #define SDIOD_DIC_EXT 0xf /* extended device interface, read ext_dev register */ 263 264 /* pwr_sel */ 265 #define SDIOD_PWR_SEL_SPS 0x01 /* supports power selection */ 266 #define SDIOD_PWR_SEL_EPS 0x02 /* enable power selection (low-current mode) */ 267 268 /* misc defines */ 269 #define SDIO_FUNC_0 0 270 #define SDIO_FUNC_1 1 271 #define SDIO_FUNC_2 2 272 #define SDIO_FUNC_3 3 273 #define SDIO_FUNC_4 4 274 #define SDIO_FUNC_5 5 275 #define SDIO_FUNC_6 6 276 #define SDIO_FUNC_7 7 277 278 #define SD_CARD_TYPE_UNKNOWN 0 /* bad type or unrecognized */ 279 #define SD_CARD_TYPE_IO 1 /* IO only card */ 280 #define SD_CARD_TYPE_MEMORY 2 /* memory only card */ 281 #define SD_CARD_TYPE_COMBO 3 /* IO and memory combo card */ 282 283 #define SDIO_MAX_BLOCK_SIZE 2048 /* maximum block size for block mode operation */ 284 #define SDIO_MIN_BLOCK_SIZE 1 /* minimum block size for block mode operation */ 285 286 /* Card registers: status bit position */ 287 #define CARDREG_STATUS_BIT_OUTOFRANGE 31 288 #define CARDREG_STATUS_BIT_COMCRCERROR 23 289 #define CARDREG_STATUS_BIT_ILLEGALCOMMAND 22 290 #define CARDREG_STATUS_BIT_ERROR 19 291 #define CARDREG_STATUS_BIT_IOCURRENTSTATE3 12 292 #define CARDREG_STATUS_BIT_IOCURRENTSTATE2 11 293 #define CARDREG_STATUS_BIT_IOCURRENTSTATE1 10 294 #define CARDREG_STATUS_BIT_IOCURRENTSTATE0 9 295 #define CARDREG_STATUS_BIT_FUN_NUM_ERROR 4 296 297 #define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */ 298 #define SD_CMD_SEND_OPCOND 1 299 #define SD_CMD_MMC_SET_RCA 3 300 #define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */ 301 #define SD_CMD_SELECT_DESELECT_CARD 7 302 #define SD_CMD_SEND_CSD 9 303 #define SD_CMD_SEND_CID 10 304 #define SD_CMD_STOP_TRANSMISSION 12 305 #define SD_CMD_SEND_STATUS 13 306 #define SD_CMD_GO_INACTIVE_STATE 15 307 #define SD_CMD_SET_BLOCKLEN 16 308 #define SD_CMD_READ_SINGLE_BLOCK 17 309 #define SD_CMD_READ_MULTIPLE_BLOCK 18 310 #define SD_CMD_WRITE_BLOCK 24 311 #define SD_CMD_WRITE_MULTIPLE_BLOCK 25 312 #define SD_CMD_PROGRAM_CSD 27 313 #define SD_CMD_SET_WRITE_PROT 28 314 #define SD_CMD_CLR_WRITE_PROT 29 315 #define SD_CMD_SEND_WRITE_PROT 30 316 #define SD_CMD_ERASE_WR_BLK_START 32 317 #define SD_CMD_ERASE_WR_BLK_END 33 318 #define SD_CMD_ERASE 38 319 #define SD_CMD_LOCK_UNLOCK 42 320 #define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */ 321 #define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */ 322 #define SD_CMD_APP_CMD 55 323 #define SD_CMD_GEN_CMD 56 324 #define SD_CMD_READ_OCR 58 325 #define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */ 326 #define SD_ACMD_SD_STATUS 13 327 #define SD_ACMD_SEND_NUM_WR_BLOCKS 22 328 #define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23 329 #define SD_ACMD_SD_SEND_OP_COND 41 330 #define SD_ACMD_SET_CLR_CARD_DETECT 42 331 #define SD_ACMD_SEND_SCR 51 332 333 /* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */ 334 #define SD_IO_OP_READ 0 /* Read_Write: Read */ 335 #define SD_IO_OP_WRITE 1 /* Read_Write: Write */ 336 #define SD_IO_RW_NORMAL 0 /* no RAW */ 337 #define SD_IO_RW_RAW 1 /* RAW */ 338 #define SD_IO_BYTE_MODE 0 /* Byte Mode */ 339 #define SD_IO_BLOCK_MODE 1 /* BlockMode */ 340 #define SD_IO_FIXED_ADDRESS 0 /* fix Address */ 341 #define SD_IO_INCREMENT_ADDRESS 1 /* IncrementAddress */ 342 343 /* build SD_CMD_IO_RW_DIRECT Argument */ 344 #define SDIO_IO_RW_DIRECT_ARG(rw, raw, func, addr, data) \ 345 ((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((raw) & 1) << 27) | \ 346 (((addr) & 0x1FFFF) << 9) | ((data) & 0xFF)) 347 348 /* build SD_CMD_IO_RW_EXTENDED Argument */ 349 #define SDIO_IO_RW_EXTENDED_ARG(rw, blk, func, addr, inc_addr, count) \ 350 ((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((blk) & 1) << 27) | \ 351 (((inc_addr) & 1) << 26) | (((addr) & 0x1FFFF) << 9) | ((count) & 0x1FF)) 352 353 /* SDIO response parameters */ 354 #define SD_RSP_NO_NONE 0 355 #define SD_RSP_NO_1 1 356 #define SD_RSP_NO_2 2 357 #define SD_RSP_NO_3 3 358 #define SD_RSP_NO_4 4 359 #define SD_RSP_NO_5 5 360 #define SD_RSP_NO_6 6 361 362 /* Modified R6 response (to CMD3) */ 363 #define SD_RSP_MR6_COM_CRC_ERROR 0x8000 364 #define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000 365 #define SD_RSP_MR6_ERROR 0x2000 366 367 /* Modified R1 in R4 Response (to CMD5) */ 368 #define SD_RSP_MR1_SBIT 0x80 369 #define SD_RSP_MR1_PARAMETER_ERROR 0x40 370 #define SD_RSP_MR1_RFU5 0x20 371 #define SD_RSP_MR1_FUNC_NUM_ERROR 0x10 372 #define SD_RSP_MR1_COM_CRC_ERROR 0x08 373 #define SD_RSP_MR1_ILLEGAL_COMMAND 0x04 374 #define SD_RSP_MR1_RFU1 0x02 375 #define SD_RSP_MR1_IDLE_STATE 0x01 376 377 /* R5 response (to CMD52 and CMD53) */ 378 #define SD_RSP_R5_COM_CRC_ERROR 0x80 379 #define SD_RSP_R5_ILLEGAL_COMMAND 0x40 380 #define SD_RSP_R5_IO_CURRENTSTATE1 0x20 381 #define SD_RSP_R5_IO_CURRENTSTATE0 0x10 382 #define SD_RSP_R5_ERROR 0x08 383 #define SD_RSP_R5_RFU 0x04 384 #define SD_RSP_R5_FUNC_NUM_ERROR 0x02 385 #define SD_RSP_R5_OUT_OF_RANGE 0x01 386 387 #define SD_RSP_R5_ERRBITS 0xCB 388 389 /* ------------------------------------------------ 390 * SDIO Commands and responses 391 * 392 * I/O only commands are: 393 * CMD0, CMD3, CMD5, CMD7, CMD14, CMD15, CMD52, CMD53 394 * ------------------------------------------------ 395 */ 396 397 /* SDIO Commands */ 398 #define SDIOH_CMD_0 0 399 #define SDIOH_CMD_3 3 400 #define SDIOH_CMD_5 5 401 #define SDIOH_CMD_7 7 402 #define SDIOH_CMD_11 11 403 #define SDIOH_CMD_14 14 404 #define SDIOH_CMD_15 15 405 #define SDIOH_CMD_19 19 406 #define SDIOH_CMD_52 52 407 #define SDIOH_CMD_53 53 408 #define SDIOH_CMD_59 59 409 410 /* SDIO Command Responses */ 411 #define SDIOH_RSP_NONE 0 412 #define SDIOH_RSP_R1 1 413 #define SDIOH_RSP_R2 2 414 #define SDIOH_RSP_R3 3 415 #define SDIOH_RSP_R4 4 416 #define SDIOH_RSP_R5 5 417 #define SDIOH_RSP_R6 6 418 419 /* 420 * SDIO Response Error flags 421 */ 422 #define SDIOH_RSP5_ERROR_FLAGS 0xCB 423 424 /* ------------------------------------------------ 425 * SDIO Command structures. I/O only commands are: 426 * 427 * CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53 428 * ------------------------------------------------ 429 */ 430 431 #define CMD5_OCR_M BITFIELD_MASK(24) 432 #define CMD5_OCR_S 0 433 434 #define CMD5_S18R_M BITFIELD_MASK(1) 435 #define CMD5_S18R_S 24 436 437 #define CMD7_RCA_M BITFIELD_MASK(16) 438 #define CMD7_RCA_S 16 439 440 #define CMD14_RCA_M BITFIELD_MASK(16) 441 #define CMD14_RCA_S 16 442 #define CMD14_SLEEP_M BITFIELD_MASK(1) 443 #define CMD14_SLEEP_S 15 444 445 #define CMD_15_RCA_M BITFIELD_MASK(16) 446 #define CMD_15_RCA_S 16 447 448 #define CMD52_DATA_M BITFIELD_MASK(8) /* Bits [7:0] - Write Data/Stuff bits of CMD52 449 */ 450 #define CMD52_DATA_S 0 451 #define CMD52_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */ 452 #define CMD52_REG_ADDR_S 9 453 #define CMD52_RAW_M BITFIELD_MASK(1) /* Bit 27 - Read after Write flag */ 454 #define CMD52_RAW_S 27 455 #define CMD52_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */ 456 #define CMD52_FUNCTION_S 28 457 #define CMD52_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */ 458 #define CMD52_RW_FLAG_S 31 459 460 #define CMD53_BYTE_BLK_CNT_M BITFIELD_MASK(9) /* Bits [8:0] - Byte/Block Count of CMD53 */ 461 #define CMD53_BYTE_BLK_CNT_S 0 462 #define CMD53_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */ 463 #define CMD53_REG_ADDR_S 9 464 #define CMD53_OP_CODE_M BITFIELD_MASK(1) /* Bit 26 - R/W Operation Code */ 465 #define CMD53_OP_CODE_S 26 466 #define CMD53_BLK_MODE_M BITFIELD_MASK(1) /* Bit 27 - Block Mode */ 467 #define CMD53_BLK_MODE_S 27 468 #define CMD53_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */ 469 #define CMD53_FUNCTION_S 28 470 #define CMD53_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */ 471 #define CMD53_RW_FLAG_S 31 472 473 /* ------------------------------------------------------ 474 * SDIO Command Response structures for SD1 and SD4 modes 475 * ----------------------------------------------------- 476 */ 477 #define RSP4_IO_OCR_M BITFIELD_MASK(24) /* Bits [23:0] - Card's OCR Bits [23:0] */ 478 #define RSP4_IO_OCR_S 0 479 480 #define RSP4_S18A_M BITFIELD_MASK(1) /* Bits [23:0] - Card's OCR Bits [23:0] */ 481 #define RSP4_S18A_S 24 482 483 #define RSP4_STUFF_M BITFIELD_MASK(3) /* Bits [26:24] - Stuff bits */ 484 #define RSP4_STUFF_S 24 485 #define RSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 27 - Memory present */ 486 #define RSP4_MEM_PRESENT_S 27 487 #define RSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [30:28] - Number of I/O funcs */ 488 #define RSP4_NUM_FUNCS_S 28 489 #define RSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 31 - SDIO card ready */ 490 #define RSP4_CARD_READY_S 31 491 492 #define RSP6_STATUS_M BITFIELD_MASK(16) /* Bits [15:0] - Card status bits [19,22,23,12:0] 493 */ 494 #define RSP6_STATUS_S 0 495 #define RSP6_IO_RCA_M BITFIELD_MASK(16) /* Bits [31:16] - RCA bits[31-16] */ 496 #define RSP6_IO_RCA_S 16 497 498 #define RSP1_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error */ 499 #define RSP1_AKE_SEQ_ERROR_S 3 500 #define RSP1_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */ 501 #define RSP1_APP_CMD_S 5 502 #define RSP1_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data (buff empty) */ 503 #define RSP1_READY_FOR_DATA_S 8 504 #define RSP1_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - State of card 505 * when Cmd was received 506 */ 507 #define RSP1_CURR_STATE_S 9 508 #define RSP1_EARSE_RESET_M BITFIELD_MASK(1) /* Bit 13 - Erase seq cleared */ 509 #define RSP1_EARSE_RESET_S 13 510 #define RSP1_CARD_ECC_DISABLE_M BITFIELD_MASK(1) /* Bit 14 - Card ECC disabled */ 511 #define RSP1_CARD_ECC_DISABLE_S 14 512 #define RSP1_WP_ERASE_SKIP_M BITFIELD_MASK(1) /* Bit 15 - Partial blocks erased due to W/P */ 513 #define RSP1_WP_ERASE_SKIP_S 15 514 #define RSP1_CID_CSD_OVERW_M BITFIELD_MASK(1) /* Bit 16 - Illegal write to CID or R/O bits 515 * of CSD 516 */ 517 #define RSP1_CID_CSD_OVERW_S 16 518 #define RSP1_ERROR_M BITFIELD_MASK(1) /* Bit 19 - General/Unknown error */ 519 #define RSP1_ERROR_S 19 520 #define RSP1_CC_ERROR_M BITFIELD_MASK(1) /* Bit 20 - Internal Card Control error */ 521 #define RSP1_CC_ERROR_S 20 522 #define RSP1_CARD_ECC_FAILED_M BITFIELD_MASK(1) /* Bit 21 - Card internal ECC failed 523 * to correct data 524 */ 525 #define RSP1_CARD_ECC_FAILED_S 21 526 #define RSP1_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 22 - Cmd not legal for the card state */ 527 #define RSP1_ILLEGAL_CMD_S 22 528 #define RSP1_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 23 - CRC check of previous command failed 529 */ 530 #define RSP1_COM_CRC_ERROR_S 23 531 #define RSP1_LOCK_UNLOCK_FAIL_M BITFIELD_MASK(1) /* Bit 24 - Card lock-unlock Cmd Seq error */ 532 #define RSP1_LOCK_UNLOCK_FAIL_S 24 533 #define RSP1_CARD_LOCKED_M BITFIELD_MASK(1) /* Bit 25 - Card locked by the host */ 534 #define RSP1_CARD_LOCKED_S 25 535 #define RSP1_WP_VIOLATION_M BITFIELD_MASK(1) /* Bit 26 - Attempt to program 536 * write-protected blocks 537 */ 538 #define RSP1_WP_VIOLATION_S 26 539 #define RSP1_ERASE_PARAM_M BITFIELD_MASK(1) /* Bit 27 - Invalid erase blocks */ 540 #define RSP1_ERASE_PARAM_S 27 541 #define RSP1_ERASE_SEQ_ERR_M BITFIELD_MASK(1) /* Bit 28 - Erase Cmd seq error */ 542 #define RSP1_ERASE_SEQ_ERR_S 28 543 #define RSP1_BLK_LEN_ERR_M BITFIELD_MASK(1) /* Bit 29 - Block length error */ 544 #define RSP1_BLK_LEN_ERR_S 29 545 #define RSP1_ADDR_ERR_M BITFIELD_MASK(1) /* Bit 30 - Misaligned address */ 546 #define RSP1_ADDR_ERR_S 30 547 #define RSP1_OUT_OF_RANGE_M BITFIELD_MASK(1) /* Bit 31 - Cmd arg was out of range */ 548 #define RSP1_OUT_OF_RANGE_S 31 549 550 #define RSP5_DATA_M BITFIELD_MASK(8) /* Bits [0:7] - data */ 551 #define RSP5_DATA_S 0 552 #define RSP5_FLAGS_M BITFIELD_MASK(8) /* Bit [15:8] - Rsp flags */ 553 #define RSP5_FLAGS_S 8 554 #define RSP5_STUFF_M BITFIELD_MASK(16) /* Bits [31:16] - Stuff bits */ 555 #define RSP5_STUFF_S 16 556 557 /* ---------------------------------------------- 558 * SDIO Command Response structures for SPI mode 559 * ---------------------------------------------- 560 */ 561 #define SPIRSP4_IO_OCR_M BITFIELD_MASK(16) /* Bits [15:0] - Card's OCR Bits [23:8] */ 562 #define SPIRSP4_IO_OCR_S 0 563 #define SPIRSP4_STUFF_M BITFIELD_MASK(3) /* Bits [18:16] - Stuff bits */ 564 #define SPIRSP4_STUFF_S 16 565 #define SPIRSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 19 - Memory present */ 566 #define SPIRSP4_MEM_PRESENT_S 19 567 #define SPIRSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [22:20] - Number of I/O funcs */ 568 #define SPIRSP4_NUM_FUNCS_S 20 569 #define SPIRSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 23 - SDIO card ready */ 570 #define SPIRSP4_CARD_READY_S 23 571 #define SPIRSP4_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - idle state */ 572 #define SPIRSP4_IDLE_STATE_S 24 573 #define SPIRSP4_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */ 574 #define SPIRSP4_ILLEGAL_CMD_S 26 575 #define SPIRSP4_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */ 576 #define SPIRSP4_COM_CRC_ERROR_S 27 577 #define SPIRSP4_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error 578 */ 579 #define SPIRSP4_FUNC_NUM_ERROR_S 28 580 #define SPIRSP4_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */ 581 #define SPIRSP4_PARAM_ERROR_S 30 582 #define SPIRSP4_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */ 583 #define SPIRSP4_START_BIT_S 31 584 585 #define SPIRSP5_DATA_M BITFIELD_MASK(8) /* Bits [23:16] - R/W Data */ 586 #define SPIRSP5_DATA_S 16 587 #define SPIRSP5_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - Idle state */ 588 #define SPIRSP5_IDLE_STATE_S 24 589 #define SPIRSP5_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */ 590 #define SPIRSP5_ILLEGAL_CMD_S 26 591 #define SPIRSP5_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */ 592 #define SPIRSP5_COM_CRC_ERROR_S 27 593 #define SPIRSP5_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error 594 */ 595 #define SPIRSP5_FUNC_NUM_ERROR_S 28 596 #define SPIRSP5_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */ 597 #define SPIRSP5_PARAM_ERROR_S 30 598 #define SPIRSP5_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */ 599 #define SPIRSP5_START_BIT_S 31 600 601 /* RSP6 card status format; Pg 68 Physical Layer spec v 1.10 */ 602 #define RSP6STAT_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error 603 */ 604 #define RSP6STAT_AKE_SEQ_ERROR_S 3 605 #define RSP6STAT_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */ 606 #define RSP6STAT_APP_CMD_S 5 607 #define RSP6STAT_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data 608 * (buff empty) 609 */ 610 #define RSP6STAT_READY_FOR_DATA_S 8 611 #define RSP6STAT_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - Card state at 612 * Cmd reception 613 */ 614 #define RSP6STAT_CURR_STATE_S 9 615 #define RSP6STAT_ERROR_M BITFIELD_MASK(1) /* Bit 13 - General/Unknown error Bit 19 616 */ 617 #define RSP6STAT_ERROR_S 13 618 #define RSP6STAT_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 14 - Illegal cmd for 619 * card state Bit 22 620 */ 621 #define RSP6STAT_ILLEGAL_CMD_S 14 622 #define RSP6STAT_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 15 - CRC previous command 623 * failed Bit 23 624 */ 625 #define RSP6STAT_COM_CRC_ERROR_S 15 626 627 #define SDIOH_XFER_TYPE_READ SD_IO_OP_READ 628 #define SDIOH_XFER_TYPE_WRITE SD_IO_OP_WRITE 629 630 /* command issue options */ 631 #define CMD_OPTION_DEFAULT 0 632 #define CMD_OPTION_TUNING 1 633 634 /* SDIO message exchange registers */ 635 #define SDIO_FN1_MSG_H2D_REG0 0x10030 636 #define SDIO_FN1_MSG_H2D_REG1 0x10034 637 #define SDIO_FN1_MSG_D2H_REG0 0x10038 638 #define SDIO_FN1_MSG_D2H_REG1 0x1003c 639 640 #define CFG_WRITE_BYTE_MASK 0xff 641 642 #define HS_POLL_PERIOD_MS 10 643 #define D2H_READY_WD_RESET_MS 1 /* 1ms */ 644 #ifdef BCMQT 645 #define D2H_READY_TIMEOUT_MS (1000 * 60 * 3) /* 3 Mins >~ FW download time */ 646 #define D2H_VALDN_DONE_TIMEOUT_MS (1000 * 60 * 5) /* 5 Mins >~ Validation time */ 647 #define D2H_TRX_HDR_PARSE_DONE_TIMEOUT_MS (1000 * 60 * 1) /* 1 Mins >~ TRX Parsing */ 648 #define D2H_READY_WD_RESET_COUNT (84 * 1000) /* ~84secs >~ BL ready time after wd rst */ 649 #define D2H_READY_WD_RESET_DBG_PRINT_MS (1000) /* 1000ms - DEBUG print at every 1000ms */ 650 #else 651 #define D2H_READY_TIMEOUT_MS (100) /* 100ms >~ FW download time */ 652 #define D2H_VALDN_DONE_TIMEOUT_MS (250) /* 250ms >~ Validation time */ 653 #define D2H_TRX_HDR_PARSE_DONE_TIMEOUT_MS (50) /* 50ms >~ TRX Parsing */ 654 #define D2H_READY_WD_RESET_COUNT (200) /* ~200ms >~ BL ready time after wd rst */ 655 #define D2H_READY_WD_RESET_DBG_PRINT_MS (10) /* 10ms - DEBUG print at evry 10ms */ 656 #endif // endif 657 658 typedef struct bl_hs_address { 659 volatile void *d2h; 660 volatile void *h2d; 661 } hs_addrs_t; 662 663 /* [D2H] Dongle to host handshake bits shift */ 664 enum { 665 D2H_START_SHIFT = 0, 666 D2H_READY_SHIFT = 1, 667 D2H_STEADY_SHIFT = 2, 668 D2H_TRX_HDR_PARSE_DONE_SHIFT = 3, 669 D2H_VALDN_START_SHIFT = 4, 670 D2H_VALDN_RESULT_SHIFT = 5, 671 D2H_VALDN_DONE_SHIFT = 6 672 /* Bits 31:7 reserved for future */ 673 }; 674 675 /* [H2D] Host to dongle handshake bits shift */ 676 enum { 677 H2D_DL_START_SHIFT = 0, 678 H2D_DL_DONE_SHIFT = 1, 679 H2D_DL_NVRAM_DONE_SHIFT = 2, 680 H2D_BL_RESET_ON_ERROR_SHIFT = 3 681 /* Bits 31:4 reserved for future */ 682 }; 683 684 #endif /* def BCMSDIO */ 685 #endif /* _SDIO_H */ 686