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Searched refs:CONFIG_DDR_PLL2 (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/cpu/arm926ejs/spear/
H A Dspr600_mt47h32m16_333_cl5_psync.c10 #if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
13 #if (CONFIG_DDR_PLL2)
H A Dspr600_mt47h64m16_3_333_cl5_psync.c10 #if (CONFIG_DDR_PLL2 || CONFIG_DDR_2HCLK)
13 #if (CONFIG_DDR_PLL2)
H A Dspr600_mt47h128m8_3_266_cl5_async.c10 #if (CONFIG_DDR_PLL2)
H A Dspear600.c85 #elif (CONFIG_DDR_PLL2) in plat_ddr_init()
H A Dspl.c39 #elif (CONFIG_DDR_PLL2) in ddr_clock_init()
/OK3568_Linux_fs/u-boot/include/configs/
H A Dx600.h253 #define CONFIG_DDR_PLL2 0 macro
/OK3568_Linux_fs/u-boot/scripts/
H A Dconfig_whitelist.txt409 CONFIG_DDR_PLL2