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Searched refs:CLK_TOP_PE2_MAC_P0_SEL (Results 1 – 4 of 4) sorted by relevance

/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dmt2712-clk.h162 #define CLK_TOP_PE2_MAC_P0_SEL 131 macro
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/
H A Dmediatek-pcie.txt156 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mt2712.c810 MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel",
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi928 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,