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Searched refs:CLK_TOP_MSDC0P_AES_SEL (Results 1 – 2 of 2) sorted by relevance

/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dmt2712-clk.h195 #define CLK_TOP_MSDC0P_AES_SEL 164 macro
/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mt2712.c884 MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel",