Searched refs:CLK_TOP_HDMIPLL_SEL (Results 1 – 2 of 2) sorted by relevance
103 #define CLK_TOP_HDMIPLL_SEL 92 macro
394 MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31),