Searched refs:CLK_PWM1_SEL_SHIFT (Results 1 – 10 of 10) sorted by relevance
| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | cru_rv1106.h | 226 CLK_PWM1_SEL_SHIFT = 9, enumerator
227 CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
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| H A D | cru_rk3528.h | 202 CLK_PWM1_SEL_SHIFT = 8, enumerator
203 CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
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| H A D | cru_rv1126.h | 181 CLK_PWM1_SEL_SHIFT = 15, enumerator
182 CLK_PWM1_SEL_MASK = 1 << CLK_PWM1_SEL_SHIFT,
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| H A D | cru_rk3588.h | 244 CLK_PWM1_SEL_SHIFT = 12, enumerator
245 CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT,
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| H A D | cru_rk3568.h | 460 CLK_PWM1_SEL_SHIFT = 8, enumerator
461 CLK_PWM1_SEL_MASK = 3 << CLK_PWM1_SEL_SHIFT,
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| /OK3568_Linux_fs/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rv1106.c | 633 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rv1106_pwm_get_clk()
677 src_clk << CLK_PWM1_SEL_SHIFT); in rv1106_pwm_set_clk()
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| H A D | clk_rv1126.c | 276 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rv1126_pwm_get_pmuclk()
317 CLK_PWM1_SEL_XIN24M << CLK_PWM1_SEL_SHIFT); in rv1126_pwm_set_pmuclk()
328 CLK_PWM1_SEL_GPLL << CLK_PWM1_SEL_SHIFT); in rv1126_pwm_set_pmuclk()
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| H A D | clk_rk3528.c | 791 shift = CLK_PWM1_SEL_SHIFT; in rk3528_pwm_get_clk()
833 shift = CLK_PWM1_SEL_SHIFT; in rk3528_pwm_set_clk()
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| H A D | clk_rk3588.c | 581 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rk3588_pwm_get_clk()
628 src_clk << CLK_PWM1_SEL_SHIFT); in rk3588_pwm_set_clk()
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| H A D | clk_rk3568.c | 1163 sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; in rk3568_pwm_get_clk()
1202 src_clk << CLK_PWM1_SEL_SHIFT); in rk3568_pwm_set_clk()
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