Searched refs:CLK_HCLK_ARM_PLL_DIV_1 (Results 1 – 2 of 2) sorted by relevance
127 case CLK_HCLK_ARM_PLL_DIV_1: in get_sdram_clk_rate()
83 #define CLK_HCLK_ARM_PLL_DIV_1 (0x0 << 0) macro