1# 2# Copyright (c) 2013-2026, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 26# the FVP platform. 27FVP_TRUSTED_SRAM_SIZE := 384 28 29# Macro to enable helpers for running SPM tests. Disabled by default. 30PLAT_TEST_SPM := 0 31 32 33# Enable passing the DT to BL33 in x0 by default. 34USE_KERNEL_DT_CONVENTION := 1 35 36# By default dont build CPUs with no FVP model. 37BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 38 39# Enable CRC instructions via extension for ARMv8-A CPUs. 40# For ARMv8.1-A, and onwards CRC instructions are default enabled. 41ifeq (${ARM_ARCH_MAJOR},8) 42ifeq (${ARM_ARCH_MINOR},0) 43 ARM_ARCH_FEATURE := crc 44endif 45endif 46ENABLE_FEAT_AMU := 2 47ENABLE_FEAT_AMUv1p1 := 2 48ENABLE_FEAT_HCX := 2 49ENABLE_FEAT_RNG := 2 50ENABLE_FEAT_TWED := 2 51ENABLE_FEAT_GCS := 2 52ENABLE_FEAT_RAS := 2 53ENABLE_FEAT_SB := 2 54 55ifeq (${ARCH}, aarch64) 56 57ifeq (${SPM_MM}, 0) 58ifeq (${CTX_INCLUDE_FPREGS}, 0) 59 ENABLE_SME_FOR_NS := 2 60 ENABLE_SME2_FOR_NS := 2 61else 62 ENABLE_SVE_FOR_NS := 0 63 ENABLE_SME_FOR_NS := 0 64 ENABLE_SME2_FOR_NS := 0 65endif 66endif 67 68 ENABLE_BRBE_FOR_NS := 2 69 ENABLE_TRBE_FOR_NS := 2 70 ENABLE_FEAT_D128 := 2 71 ENABLE_FEAT_FPMR := 2 72 ENABLE_FEAT_MOPS := 2 73 ENABLE_FEAT_FGWTE3 := 2 74 ENABLE_FEAT_MPAM_PE_BW_CTRL := 2 75 ENABLE_FEAT_CPA2 := 2 76 ENABLE_FEAT_UINJ := 2 77 ENABLE_FEAT_STEP2 := 2 78 ENABLE_FEAT_HDBSS := 2 79 ENABLE_FEAT_HACDBS := 2 80endif 81 82ENABLE_SYS_REG_TRACE_FOR_NS := 2 83ENABLE_FEAT_CSV2_2 := 2 84ENABLE_FEAT_CSV2_3 := 2 85ENABLE_FEAT_CLRBHB := 2 86ENABLE_FEAT_DEBUGV8P9 := 2 87ENABLE_FEAT_DIT := 2 88ENABLE_FEAT_PAN := 2 89ENABLE_FEAT_VHE := 2 90CTX_INCLUDE_NEVE_REGS := 2 91ENABLE_FEAT_SEL2 := 2 92ENABLE_TRF_FOR_NS := 2 93ENABLE_FEAT_ECV := 2 94ENABLE_FEAT_FGT := 2 95ENABLE_FEAT_FGT2 := 2 96ENABLE_FEAT_THE := 2 97ENABLE_FEAT_TCR2 := 2 98ENABLE_FEAT_S2PIE := 2 99ENABLE_FEAT_S1PIE := 2 100ENABLE_FEAT_S2POE := 2 101ENABLE_FEAT_S1POE := 2 102ENABLE_FEAT_SCTLR2 := 2 103ENABLE_FEAT_MTE2 := 2 104ENABLE_FEAT_LS64_ACCDATA := 2 105ENABLE_FEAT_AIE := 2 106ENABLE_FEAT_PFAR := 2 107ENABLE_FEAT_EBEP := 2 108 109ifeq (${ENABLE_RMM},1) 110 ENABLE_FEAT_MEC := 2 111 RMMD_ENABLE_IDE_KEY_PROG := 1 112endif 113 114# always check that hardware matches the codebase's expectations 115FEATURE_DETECTION := 1 116 117# The FVP platform depends on this macro to build with correct GIC driver. 118$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 119 120# Pass FVP_CLUSTER_COUNT to the build system. 121$(eval $(call add_define,FVP_CLUSTER_COUNT)) 122 123# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 124$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 125 126# Pass FVP_MAX_PE_PER_CPU to the build system. 127$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 128 129# Pass FVP_GICR_REGION_PROTECTION to the build system. 130$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 131 132# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 133$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 134 135ifeq (${DRTM_SUPPORT},1) 136MBOOT_EL_HASH_ALG := sha256 137endif 138 139# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 140# choose the CCI driver , else the CCN driver 141ifeq ($(FVP_CLUSTER_COUNT), 0) 142$(error "Incorrect cluster count specified for FVP port") 143else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 144FVP_INTERCONNECT_DRIVER := FVP_CCI 145else 146FVP_INTERCONNECT_DRIVER := FVP_CCN 147endif 148 149$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 150 151ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 152include_fconf_srcs = 1 153endif 154 155ifneq ($(filter 1,${ARM_FW_CONFIG_LOAD_ENABLE} ${TRANSFER_LIST} ${ENABLE_RMM}),) 156include_fconf_srcs = 1 157endif 158 159# Choose the GIC sources depending upon the how the FVP will be invoked 160ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 161USE_GIC_DRIVER := 3 162 163# The GIC model (GIC-600 or GIC-500) will be detected at runtime 164GICV3_SUPPORT_GIC600 := 1 165GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 166 167FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 168 169ifdef include_fconf_srcs 170BL31_SOURCES += plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c 171endif 172 173ifeq (${HW_ASSISTED_COHERENCY}, 0) 174FVP_DT_PREFIX := fvp-base-gicv3-psci 175else 176FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 177endif 178else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5) 179USE_GIC_DRIVER := 5 180ENABLE_FEAT_GCIE := 1 181BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c 182FVP_DT_PREFIX := fvp-base-gicv5-psci 183ifneq ($(SPD),none) 184 $(error Error: GICv5 is not compatible with SPDs) 185endif 186ifeq ($(ENABLE_RMM),1) 187 $(error Error: GICv5 is not compatible with RME) 188endif 189else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 190USE_GIC_DRIVER := 2 191 192# No GICv4 extension 193GIC_ENABLE_V4_EXTN := 0 194$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 195 196FVP_DT_PREFIX := fvp-base-gicv2-psci 197else 198$(error "Incorrect GIC driver chosen on FVP port") 199endif 200 201ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 202FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 203else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 204FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 205 plat/arm/common/arm_ccn.c 206else 207$(error "Incorrect CCN driver chosen on FVP port") 208endif 209 210FVP_SECURITY_SOURCES += drivers/arm/tzc/tzc400.c \ 211 plat/arm/board/fvp/fvp_security.c \ 212 plat/arm/common/arm_tzc400.c 213 214 215PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 216 -Iinclude/lib/psa 217 218 219PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 220 221FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 222 223ifeq (${ARCH}, aarch64) 224 225# select a different set of CPU files, depending on whether we compile for 226# hardware assisted coherency cores or not 227ifeq (${HW_ASSISTED_COHERENCY}, 0) 228# Cores used without DSU 229 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 230 lib/cpus/aarch64/cortex_a53.S \ 231 lib/cpus/aarch64/cortex_a57.S \ 232 lib/cpus/aarch64/cortex_a72.S \ 233 lib/cpus/aarch64/cortex_a73.S 234else 235# Cores used with DSU only 236 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 237 # AArch64-only cores 238 # TODO: add all cores to the appropriate lists 239 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 240 lib/cpus/aarch64/cortex_a65ae.S \ 241 lib/cpus/aarch64/cortex_a76.S \ 242 lib/cpus/aarch64/cortex_a76ae.S \ 243 lib/cpus/aarch64/cortex_a77.S \ 244 lib/cpus/aarch64/cortex_a78.S \ 245 lib/cpus/aarch64/cortex_a78_ae.S \ 246 lib/cpus/aarch64/cortex_a78c.S \ 247 lib/cpus/aarch64/cortex_a710.S \ 248 lib/cpus/aarch64/cortex_a715.S \ 249 lib/cpus/aarch64/cortex_a720.S \ 250 lib/cpus/aarch64/cortex_a720_ae.S \ 251 lib/cpus/aarch64/neoverse_n1.S \ 252 lib/cpus/aarch64/neoverse_n2.S \ 253 lib/cpus/aarch64/neoverse_v1.S \ 254 lib/cpus/aarch64/neoverse_e1.S \ 255 lib/cpus/aarch64/cortex_x2.S \ 256 lib/cpus/aarch64/cortex_x4.S 257 endif 258 # AArch64/AArch32 cores 259 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 260 lib/cpus/aarch64/cortex_a75.S 261endif 262 263#Include all CPUs to build to support all-errata build. 264ifeq (${ENABLE_ERRATA_ALL},1) 265 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 266 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 267 lib/cpus/aarch64/cortex_a510.S \ 268 lib/cpus/aarch64/cortex_a520.S \ 269 lib/cpus/aarch64/cortex_a725.S \ 270 lib/cpus/aarch64/cortex_x1.S \ 271 lib/cpus/aarch64/cortex_x3.S \ 272 lib/cpus/aarch64/cortex_x925.S \ 273 lib/cpus/aarch64/neoverse_n3.S \ 274 lib/cpus/aarch64/neoverse_v2.S \ 275 lib/cpus/aarch64/neoverse_v3.S 276endif 277 278#Build AArch64-only CPUs with no FVP model yet. 279ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 280 FVP_CPU_LIBS += lib/cpus/aarch64/c1_pro.S \ 281 lib/cpus/aarch64/c1_nano.S \ 282 lib/cpus/aarch64/c1_ultra.S \ 283 lib/cpus/aarch64/c1_premium.S \ 284 lib/cpus/aarch64/canyon.S \ 285 lib/cpus/aarch64/caddo.S \ 286 lib/cpus/aarch64/rosillo.S \ 287 lib/cpus/aarch64/veymont.S \ 288 lib/cpus/aarch64/dionysus.S \ 289 lib/cpus/aarch64/venom.S \ 290 lib/cpus/aarch64/lsc25_p_core.S \ 291 lib/cpus/aarch64/lsc25_e_core.S 292endif 293 294else 295FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 296 lib/cpus/aarch32/cortex_a57.S \ 297 lib/cpus/aarch32/cortex_a53.S 298endif 299 300BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 301 drivers/arm/sp805/sp805.c \ 302 drivers/delay_timer/delay_timer.c \ 303 drivers/io/io_semihosting.c \ 304 lib/semihosting/semihosting.c \ 305 lib/semihosting/${ARCH}/semihosting_call.S \ 306 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 307 plat/arm/board/fvp/fvp_bl1_setup.c \ 308 plat/arm/board/fvp/fvp_cpu_pwr.c \ 309 plat/arm/board/fvp/fvp_err.c \ 310 plat/arm/board/fvp/fvp_io_storage.c \ 311 plat/arm/board/fvp/fvp_topology.c \ 312 ${FVP_CPU_LIBS} \ 313 ${FVP_INTERCONNECT_SOURCES} 314 315ifeq (${USE_SP804_TIMER},1) 316BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 317else 318BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 319endif 320 321 322BL2_SOURCES += drivers/arm/sp805/sp805.c \ 323 drivers/io/io_semihosting.c \ 324 lib/utils/mem_region.c \ 325 lib/semihosting/semihosting.c \ 326 lib/semihosting/${ARCH}/semihosting_call.S \ 327 plat/arm/board/fvp/fvp_bl2_setup.c \ 328 plat/arm/board/fvp/fvp_err.c \ 329 plat/arm/board/fvp/fvp_io_storage.c \ 330 plat/arm/common/arm_nor_psci_mem_protect.c \ 331 ${FVP_SECURITY_SOURCES} 332 333 334ifeq (${COT_DESC_IN_DTB},1) 335BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 336endif 337 338ifeq (${ENABLE_RMM},1) 339BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 340 plat/arm/board/fvp/fvp_cpu_pwr.c 341 342BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 343 plat/arm/board/fvp/fvp_realm_attest_key.c \ 344 plat/arm/board/fvp/fvp_el3_token_sign.c \ 345 plat/arm/board/fvp/fvp_ide_keymgmt.c \ 346 plat/arm/common/plat_rmm_mem_carveout.c 347endif 348 349ifneq (${ENABLE_FEAT_RNG_TRAP},0) 350BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 351endif 352 353ifeq (${RESET_TO_BL2},1) 354BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 355 plat/arm/board/fvp/fvp_cpu_pwr.c \ 356 ${FVP_CPU_LIBS} \ 357 ${FVP_INTERCONNECT_SOURCES} 358endif 359 360ifeq (${USE_SP804_TIMER},1) 361BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 362endif 363 364BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 365 ${FVP_SECURITY_SOURCES} 366 367ifeq (${USE_SP804_TIMER},1) 368BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 369endif 370 371BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 372 drivers/arm/smmu/smmu_v3.c \ 373 drivers/delay_timer/delay_timer.c \ 374 drivers/cfi/v2m/v2m_flash.c \ 375 lib/utils/mem_region.c \ 376 plat/arm/board/fvp/fvp_bl31_setup.c \ 377 plat/arm/board/fvp/fvp_console.c \ 378 plat/arm/board/fvp/fvp_pm.c \ 379 plat/arm/board/fvp/fvp_topology.c \ 380 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 381 plat/arm/board/fvp/fvp_cpu_pwr.c \ 382 plat/arm/common/arm_nor_psci_mem_protect.c \ 383 ${FVP_CPU_LIBS} \ 384 ${FVP_INTERCONNECT_SOURCES} \ 385 ${FVP_SECURITY_SOURCES} 386 387# Support for fconf in BL31 388# Added separately from the above list for better readability 389ifdef include_fconf_srcs 390BL31_SOURCES += lib/fconf/fconf.c \ 391 lib/fconf/fconf_dyn_cfg_getter.c \ 392 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 393 394BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 395 396ifeq (${SEC_INT_DESC_IN_FCONF},1) 397BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 398endif 399 400endif 401 402ifeq (${USE_SP804_TIMER},1) 403BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 404else 405BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 406endif 407 408# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 409FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 410 411FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 412$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 413HW_CONFIG := ${FVP_HW_CONFIG} 414 415HW_CONFIG_BASE ?= 0x82000000 416 417# Set default initrd base 128MiB offset of the default kernel address in FVP 418INITRD_BASE ?= 0x90000000 419 420# Kernel base address supports Linux kernels before v5.7 421# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 422ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 423 PRELOADED_BL33_BASE ?= 0x80080000 424 ifeq (${RESET_TO_BL31},1) 425 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 426 endif 427endif 428 429ifeq (${TRANSFER_LIST}, 0) 430FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 431 ${PLAT}_fw_config.dts \ 432 ${PLAT}_tb_fw_config.dts \ 433 ${PLAT}_soc_fw_config.dts \ 434 ${PLAT}_nt_fw_config.dts \ 435 ) 436 437FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 438FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 439FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 440FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 441 442ifeq (${SPD},tspd) 443FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 444FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 445 446# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 447$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 448endif 449 450# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 451$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 452# Add the NT_FW_CONFIG to FIP and specify the same to certtool 453$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 454endif 455 456ifeq (${SPD},spmd) 457 458ifeq ($(ARM_SPMC_MANIFEST_DTS),) 459ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 460endif 461 462FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 463FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 464 465# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 466$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 467endif 468 469# Add the HW_CONFIG to FIP and specify the same to certtool 470$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 471 472ifeq (${TRANSFER_LIST}, 1) 473 474ifeq ($(RESET_TO_BL31), 1) 475FW_HANDOFF_SIZE := 20000 476 477TRANSFER_LIST_DTB_OFFSET := 0x20 478$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 479endif 480 481# 482# To load SP_PKGs with TRANSFER_LIST, FVP_TB_FW_CONFIG is required. 483# 484ifeq (${BL2_ENABLE_SP_LOAD}, 1) 485 FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 486 ${PLAT}_tb_fw_config.dts \ 487 ) 488 489 FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 490 491 # Add the TB_FW_CONFIG to FIP and specify the same to certtool 492 $(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 493endif 494 495endif 496 497ifeq (${HOB_LIST}, 1) 498include lib/hob/hob.mk 499endif 500 501# Enable dynamic mitigation support by default 502DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 503 504ifneq (${ENABLE_FEAT_AMU},0) 505BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 506 lib/cpus/aarch64/cpuamu_helpers.S 507 508ifeq (${HW_ASSISTED_COHERENCY}, 1) 509BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 510 lib/cpus/aarch64/neoverse_n1_pubsub.c 511endif 512endif 513 514ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 515 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 516 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 517 endif 518 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c \ 519 plat/arm/board/fvp/aarch64/fvp_ea.c 520endif 521 522ifneq (${ENABLE_STACK_PROTECTOR},0) 523PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 524endif 525 526# Enable the dynamic translation tables library. 527ifneq (${ARM_XLAT_TABLES_LIB_V1},1) 528 ifeq (${ARCH},aarch32) 529 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 530 else # AArch64 531 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 532 endif 533endif 534 535ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 536 ifeq (${ARCH},aarch32) 537 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 538 else # AArch64 539 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 540 ifeq (${SPD},tspd) 541 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 542 endif 543 endif 544endif 545 546ifeq (${USE_DEBUGFS},1) 547 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 548endif 549 550# Add support for platform supplied linker script for BL31 build 551PLAT_EXTRA_LD_SCRIPT := 1 552 553ifneq (${RESET_TO_BL2}, 0) 554 override BL1_SOURCES = 555endif 556 557include plat/arm/board/common/board_common.mk 558include plat/arm/common/arm_common.mk 559 560ifeq (${MEASURED_BOOT},1) 561BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 562 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 563 lib/psa/measured_boot.c \ 564 common/measured_boot_helpers.c 565 566BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 567 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 568 lib/psa/measured_boot.c \ 569 common/measured_boot_helpers.c 570endif 571 572ifeq (${DRTM_SUPPORT}, 1) 573BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 574 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 575 plat/arm/board/fvp/fvp_drtm_err.c \ 576 plat/arm/board/fvp/fvp_drtm_measurement.c \ 577 plat/arm/board/fvp/fvp_drtm_stub.c \ 578 plat/arm/common/arm_dyn_cfg.c \ 579 plat/arm/board/fvp/fvp_err.c 580endif 581 582ifeq (${TRUSTED_BOARD_BOOT}, 1) 583BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 584BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 585 586# FVP being a development platform, enable capability to disable Authentication 587# dynamically if TRUSTED_BOARD_BOOT is set. 588DYN_DISABLE_AUTH := 1 589endif 590 591ifeq (${SPMC_AT_EL3}, 1) 592PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 593endif 594 595PSCI_OS_INIT_MODE := 1 596 597ifeq (${SPD},spmd) 598BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 599endif 600 601# Test specific macros, keep them at bottom of this file 602$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 603ifeq (${PLATFORM_TEST_EA_FFH}, 1) 604 ifeq (${FFH_SUPPORT}, 0) 605 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 606 endif 607 608endif 609 610PLATFORM_TEST_RAS_FFH ?= 0 611$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 612ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 613 ifeq (${ENABLE_FEAT_RAS}, 0) 614 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 615 endif 616 ifeq (${SDEI_SUPPORT}, 0) 617 $(error "PLATFORM_TEST_RAS_FFH expects SDEI_SUPPORT to be 1") 618 endif 619 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 620 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 621 endif 622endif 623 624$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 625ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 626 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 627 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 628 endif 629 ifeq (${ENABLE_SPMD_LP}, 0) 630 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 631 endif 632 ifeq (${ENABLE_FEAT_RAS}, 0) 633 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 634 endif 635 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 636 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 637 endif 638endif 639 640ifeq (${ERRATA_ABI_SUPPORT}, 1) 641include plat/arm/board/fvp/fvp_cpu_errata.mk 642endif 643 644# Build macro necessary for running SPM tests on FVP platform 645$(eval $(call add_define,PLAT_TEST_SPM)) 646 647ifeq (${LFA_SUPPORT},1) 648BL31_SOURCES += plat/arm/board/fvp/fvp_lfa.c 649endif 650 651# This is set to 1 by default when the firmware update 652# support is enabled. Since the BL2 image is not updatable 653ifeq ($(PSA_FWU_SUPPORT),1) 654 SEPARATE_BL2_FIP := 1 655endif 656 657ifeq (${TRANSFER_LIST}, 0) 658ifeq (${SEPARATE_BL2_FIP},1) 659$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG},BL2_)) 660$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG},BL2_)) 661else 662$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 663$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 664endif 665endif 666 667ifeq ($(ARM_FW_CONFIG_LOAD_ENABLE)-$(TRUSTED_BOARD_BOOT),1-1) 668$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert)) 669endif 670