Searched hist:fe06e118ab0837ff173f6b7e576dcc34b2d26bb1 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_x2.S | fe06e118ab0837ff173f6b7e576dcc34b2d26bb1 Tue Oct 17 14:11:19 UTC 2023 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-X2 erratum 2742423
Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest
Change-Id: I03897dc2a7f908937612c2b66ce7a043c1b7575d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
|
| /rk3399_ARM-atf/services/std_svc/errata_abi/ |
| H A D | errata_abi_main.c | fe06e118ab0837ff173f6b7e576dcc34b2d26bb1 Tue Oct 17 14:11:19 UTC 2023 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-X2 erratum 2742423
Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest
Change-Id: I03897dc2a7f908937612c2b66ce7a043c1b7575d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | fe06e118ab0837ff173f6b7e576dcc34b2d26bb1 Tue Oct 17 14:11:19 UTC 2023 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-X2 erratum 2742423
Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest
Change-Id: I03897dc2a7f908937612c2b66ce7a043c1b7575d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | fe06e118ab0837ff173f6b7e576dcc34b2d26bb1 Tue Oct 17 14:11:19 UTC 2023 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-X2 erratum 2742423
Cortex-X2 erratum 2742423 is a Cat B erratum that applies to all
revisions <= r2p1 and is still open.
The workaround is to set CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest
Change-Id: I03897dc2a7f908937612c2b66ce7a043c1b7575d
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
|