Searched hist:ef934cd17c30dcc39cd9022a1c4e9523ec8ba617 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a710.h | ef934cd17c30dcc39cd9022a1c4e9523ec8ba617 Tue Mar 01 00:34:04 UTC 2022 johpow01 <john.powell@arm.com> fix(errata): workaround for Cortex-A710 2282622
Cortex-A710 erratum 2282622 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR2_EL1[0] to 1, which will force PLDW/PFRM ST to behave like
PLD/PRFM LD and not cause invalidations to other PE caches.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic48409822536e9eacc003300036a1f0489593020
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a710.S | ef934cd17c30dcc39cd9022a1c4e9523ec8ba617 Tue Mar 01 00:34:04 UTC 2022 johpow01 <john.powell@arm.com> fix(errata): workaround for Cortex-A710 2282622
Cortex-A710 erratum 2282622 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR2_EL1[0] to 1, which will force PLDW/PFRM ST to behave like
PLD/PRFM LD and not cause invalidations to other PE caches.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic48409822536e9eacc003300036a1f0489593020
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | ef934cd17c30dcc39cd9022a1c4e9523ec8ba617 Tue Mar 01 00:34:04 UTC 2022 johpow01 <john.powell@arm.com> fix(errata): workaround for Cortex-A710 2282622
Cortex-A710 erratum 2282622 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR2_EL1[0] to 1, which will force PLDW/PFRM ST to behave like
PLD/PRFM LD and not cause invalidations to other PE caches.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic48409822536e9eacc003300036a1f0489593020
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | ef934cd17c30dcc39cd9022a1c4e9523ec8ba617 Tue Mar 01 00:34:04 UTC 2022 johpow01 <john.powell@arm.com> fix(errata): workaround for Cortex-A710 2282622
Cortex-A710 erratum 2282622 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set
CPUACTLR2_EL1[0] to 1, which will force PLDW/PFRM ST to behave like
PLD/PRFM LD and not cause invalidations to other PE caches.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic48409822536e9eacc003300036a1f0489593020
|