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/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_clock_manager.he60bedd5e134e2ad996a0d21a8170caec12c2dd2 Fri Oct 25 01:22:00 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> feat(intel): clock manager PLL configuration for Agilex5 platform

Read the hand-off data and configure the clock manager main
and peripheral PLL and few other misc updates.

Change-Id: I3c5cbaf7a677a022ef24b0e679860e6ee195f16a
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_clock_manager.ce60bedd5e134e2ad996a0d21a8170caec12c2dd2 Fri Oct 25 01:22:00 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> feat(intel): clock manager PLL configuration for Agilex5 platform

Read the hand-off data and configure the clock manager main
and peripheral PLL and few other misc updates.

Change-Id: I3c5cbaf7a677a022ef24b0e679860e6ee195f16a
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
/rk3399_ARM-atf/plat/intel/soc/agilex5/
H A Dbl2_plat_setup.ce60bedd5e134e2ad996a0d21a8170caec12c2dd2 Fri Oct 25 01:22:00 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> feat(intel): clock manager PLL configuration for Agilex5 platform

Read the hand-off data and configure the clock manager main
and peripheral PLL and few other misc updates.

Change-Id: I3c5cbaf7a677a022ef24b0e679860e6ee195f16a
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>