Searched hist:e4462dae81d0674eaf07ad8fa61b25b28a209d0b (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/include/ |
| H A D | platform_def.h | e4462dae81d0674eaf07ad8fa61b25b28a209d0b Tue Aug 06 10:25:51 UTC 2024 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> feat(nxp-clk): enable UART clock
Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.
Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
|
| /rk3399_ARM-atf/include/drivers/nxp/clk/s32cc/ |
| H A D | s32cc-clk-ids.h | e4462dae81d0674eaf07ad8fa61b25b28a209d0b Tue Aug 06 10:25:51 UTC 2024 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> feat(nxp-clk): enable UART clock
Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.
Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
|
| /rk3399_ARM-atf/drivers/nxp/clk/s32cc/ |
| H A D | s32cc_clk_modules.c | e4462dae81d0674eaf07ad8fa61b25b28a209d0b Tue Aug 06 10:25:51 UTC 2024 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> feat(nxp-clk): enable UART clock
Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.
Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
|
| H A D | s32cc_early_clks.c | e4462dae81d0674eaf07ad8fa61b25b28a209d0b Tue Aug 06 10:25:51 UTC 2024 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> feat(nxp-clk): enable UART clock
Before this change, the internal oscillator clocked the UART with a
frequency of 48MHz. With the necessary support added, the UART clock
rate is increased to 125MHz by changing the clock source from FIRC to
PERIPH PLL PHI3.
Change-Id: I3160dc6860ebf441c9bea8eaf9d8d12de48bd647
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
|