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/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3188.hdcb51bfed1fa3950f9f561b08f5d9b667999fafc Mon Oct 16 06:56:21 UTC 2017 David Wu <david.wu@rock-chips.com> clk: rockchip: Add rk3188 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Change-Id: I1869cd06615e037548e77eae65df4acdf666a058
Signed-off-by: David Wu <david.wu@rock-chips.com>
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3188.cdcb51bfed1fa3950f9f561b08f5d9b667999fafc Mon Oct 16 06:56:21 UTC 2017 David Wu <david.wu@rock-chips.com> clk: rockchip: Add rk3188 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Change-Id: I1869cd06615e037548e77eae65df4acdf666a058
Signed-off-by: David Wu <david.wu@rock-chips.com>