Searched hist:cdb6babec6422ad4b89e447b1b468f625deaea79 (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/arch/x86/dts/ |
| H A D | crownbay.dts | cdb6babec6422ad4b89e447b1b468f625deaea79 Tue Jun 23 04:18:55 UTC 2015 Bin Meng <bmeng.cn@gmail.com> x86: queensbay: Change PCIe root ports' interrupt routing
So far interrupt routing works pretty well for any on-chip devices
on Intel Crown Bay. When inserting any PCIe card to any PCIe slot,
Linux kernel is smart enough to do interrupt swizzling and figure
out device's irq using its parent bridge's interrupt routing info
all the way up to its root port. In U-Boot all PCIe root ports'
interrupts were routed to PIRQ E/F/G/H before, while actually all
PCIe downstream ports received INTx are routed to PIRQ A/B/C/D
directly and not configurable. Now we change this mapping so that
any external PCIe device can work correctly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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| /rk3399_rockchip-uboot/arch/x86/cpu/queensbay/ |
| H A D | tnc.c | cdb6babec6422ad4b89e447b1b468f625deaea79 Tue Jun 23 04:18:55 UTC 2015 Bin Meng <bmeng.cn@gmail.com> x86: queensbay: Change PCIe root ports' interrupt routing
So far interrupt routing works pretty well for any on-chip devices
on Intel Crown Bay. When inserting any PCIe card to any PCIe slot,
Linux kernel is smart enough to do interrupt swizzling and figure
out device's irq using its parent bridge's interrupt routing info
all the way up to its root port. In U-Boot all PCIe root ports'
interrupts were routed to PIRQ E/F/G/H before, while actually all
PCIe downstream ports received INTx are routed to PIRQ A/B/C/D
directly and not configurable. Now we change this mapping so that
any external PCIe device can work correctly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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