Merge git://git.denx.de/u-boot-dm

dm: core: Add flags parameter to device_remove()

This patch adds the flags parameter to device_remove() and changes all
calls to this function to provide the default value of DM_REMOVE_NORMAL
for "n

dm: core: Add flags parameter to device_remove()

This patch adds the flags parameter to device_remove() and changes all
calls to this function to provide the default value of DM_REMOVE_NORMAL
for "normal" device removal.

This is in preparation for the driver specific pre-OS (e.g. DMA
cancelling) remove support.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>

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x86: squash lines for immediate return

arch_cpu_init() can be simpler by this refactoring.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

x86: squash lines for immediate return

arch_cpu_init() can be simpler by this refactoring.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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x86: tnc: Remove IGD and SDVO devices from driver model

With recent DM PCI changes to vesa_fb driver, external graphics
card does not work any more. This is because: after setting the
function disab

x86: tnc: Remove IGD and SDVO devices from driver model

With recent DM PCI changes to vesa_fb driver, external graphics
card does not work any more. This is because: after setting the
function disable bit, IGD and SDVO devices will disappear in the
PCI configuration space. This however creates an inconsistent state
from a driver model PCI controller point of view, as these two PCI
devices are still attached to its parent's child device list as
maintained by the driver model. Some driver model PCI APIs like
dm_pci_find_class() used in the vesa_fb driver, are referring to
the list to speed up the finding process instead of re-enumerating
the whole PCI bus, so it gets the stale cached data which is wrong.

To fix this, manually remove these two devices.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

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x86: tnc: Use DM PCI API in disable_igd()

Once we get udevice of IGD and SDVO, we can use its udevice to
access PCI configuration space with dm_pci_write_config32().

Signed-off-by: Bin Meng <bmeng.

x86: tnc: Use DM PCI API in disable_igd()

Once we get udevice of IGD and SDVO, we can use its udevice to
access PCI configuration space with dm_pci_write_config32().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

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x86: tnc: Change disable_igd() to have a return value

So far disable_igd() does not have any return value, but we may need
that in the future.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-

x86: tnc: Change disable_igd() to have a return value

So far disable_igd() does not have any return value, but we may need
that in the future.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

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x86: tnc: Drop unprotect_spi_flash()

Unprotecting SPI flash is now handled in the SPI controller driver,
via a call to the PCH driver. Drop the ad-hoc version.

Signed-off-by: Bin Meng <bmeng.cn@gma

x86: tnc: Drop unprotect_spi_flash()

Unprotecting SPI flash is now handled in the SPI controller driver,
via a call to the PCH driver. Drop the ad-hoc version.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

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dm: x86: queensbay: Add an interrupt driver

Add a driver for interrupts on queensbay and move the code currently in
cpu_irq_init() into its probe() method.

Signed-off-by: Simon Glass <sjg@chromium.

dm: x86: queensbay: Add an interrupt driver

Add a driver for interrupts on queensbay and move the code currently in
cpu_irq_init() into its probe() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

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dm: x86: Set up interrupt routing from interrupt_init()

At present interrupt routing is set up from arch_misc_init(). We can do it
a little later instead, in interrupt_init().

This removes the manu

dm: x86: Set up interrupt routing from interrupt_init()

At present interrupt routing is set up from arch_misc_init(). We can do it
a little later instead, in interrupt_init().

This removes the manual pirq_init() call. Where the platform does not have
an interrupt router defined in its device tree, no error is generated. Some
platforms do not have this.

Drop pirq_init() since it is no-longer used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

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x86: Convert to use driver model timer

Convert all x86 boards to use driver model tsc timer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

Merge branch 'master' of git://git.denx.de/u-boot-x86

x86: queensbay: Really disable IGD

According to Atom E6xx datasheet, setting VGA Disable (bit17)
of Graphics Controller register (offset 0x50) prevents IGD
(D2:F0) from reporting itself as a VGA dis

x86: queensbay: Really disable IGD

According to Atom E6xx datasheet, setting VGA Disable (bit17)
of Graphics Controller register (offset 0x50) prevents IGD
(D2:F0) from reporting itself as a VGA display controller
class in the PCI configuration space, and should also prevent
it from responding to VGA legacy memory range and I/O addresses.

However test result shows that with just VGA Disable bit set and
a PCIe graphics card connected to one of the PCIe controllers on
the E6xx, accessing the VGA legacy space still causes system hang.
After a number of attempts, it turns out besides VGA Disable bit,
the SDVO (D3:F0) device should be disabled to make it work.

To simplify, use the Function Disable register (offset 0xc4)
to disable both IGD (D2:F0) and SDVO (D3:F0) devices. Now these
two devices will be completely disabled (invisible in the PCI
configuration space) unless a system reset is performed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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Merge branch 'master' of git://git.denx.de/u-boot

Merge git://git.denx.de/u-boot-x86

x86: Allow disabling IGD on Intel Queensbay

Add a Kconfig option to disable the Integrated Graphics Device (IGD)
so that it does not show in the PCI configuration space as a VGA
disaplay controller.

x86: Allow disabling IGD on Intel Queensbay

Add a Kconfig option to disable the Integrated Graphics Device (IGD)
so that it does not show in the PCI configuration space as a VGA
disaplay controller. This gives a chance for U-Boot to run PCI/PCIe
based graphics card's VGA BIOS and use that for the graphics console.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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Merge git://git.denx.de/u-boot-x86

x86: queensbay: Move unprotect_spi_flash() to arch_misc_init()

With dm pci conversion, pci config read/write in unprotect_spi_flash()
silently fails as at that time dm pci is not ready and bus enume

x86: queensbay: Move unprotect_spi_flash() to arch_misc_init()

With dm pci conversion, pci config read/write in unprotect_spi_flash()
silently fails as at that time dm pci is not ready and bus enumeration
is not done yet. Actually we don't need to do this in that early phase,
hence we delay this call to arch_misc_init().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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Merge git://git.denx.de/u-boot-x86

x86: Allow pirq_init() to return an error

This function can fail. In this case we should return the error rather than
swallowing it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin M

x86: Allow pirq_init() to return an error

This function can fail. In this case we should return the error rather than
swallowing it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: Convert to use driver model pci on queensbay/crownbay

Move to driver model pci for Intel queensbay/crownbay.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Merge branch 'master' of git://git.denx.de/u-boot

Merge git://git.denx.de/u-boot-x86

x86: queensbay: Change PCIe root ports' interrupt routing

So far interrupt routing works pretty well for any on-chip devices
on Intel Crown Bay. When inserting any PCIe card to any PCIe slot,
Linux

x86: queensbay: Change PCIe root ports' interrupt routing

So far interrupt routing works pretty well for any on-chip devices
on Intel Crown Bay. When inserting any PCIe card to any PCIe slot,
Linux kernel is smart enough to do interrupt swizzling and figure
out device's irq using its parent bridge's interrupt routing info
all the way up to its root port. In U-Boot all PCIe root ports'
interrupts were routed to PIRQ E/F/G/H before, while actually all
PCIe downstream ports received INTx are routed to PIRQ A/B/C/D
directly and not configurable. Now we change this mapping so that
any external PCIe device can work correctly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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Merge branch 'u-boot/master' into 'u-boot-arm/master'

x86: Refactor PIRQ routing support

PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memor

x86: Refactor PIRQ routing support

PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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