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| H A D | rockchip_sfc.c | cbd9216dad6e8e09917866ba7ee2afa25c30ed34 Tue May 19 15:35:42 UTC 2020 Jon Lin <jon.lin@rock-chips.com> spi: rockchip_sfc: Change SPI Nand dummy cycles as X8bits address
Spetial patch for GD devices cause u-boot SPI Nand MTD bad
supporting for GD, and the u-boot mainline haven't synchronize
with Linux.
reference to following Linux commit:
commit f1541773af49ecd1edae29c8ac0775253a0b0760
Author: Chuanhong Guo <gch981213@gmail.com>
Date: Sat Feb 8 15:43:50 2020 +0800
mtd: spinand: rework detect procedure for different READ_ID operation
Currently there are 3 different variants of read_id implementation:
1. opcode only. Found in GD5FxGQ4xF.
2. opcode + 1 addr byte. Found in GD5GxGQ4xA/E
3. opcode + 1 dummy byte. Found in other currently supported chips.
Original implementation was for variant 1 and let detect function
of chips with variant 2 and 3 to ignore the first byte. This isn't
robust:
1. For chips of variant 2, if SPI master doesn't keep MOSI low
during read, chip will get a random id offset, and the entire id
buffer will shift by that offset, causing detect failure.
2. For chips of variant 1, if it happens to get a devid that equals
to manufacture id of variant 2 or 3 chips, it'll get incorrectly
detected.
This patch reworks detect procedure to address problems above. New
logic do detection for all variants separatedly, in 1-2-3 order.
Since all current detect methods do exactly the same id matching
procedure, unify them into core.c and remove detect method from
manufacture_ops.
Change-Id: If60d0281eb963486639d5b4ce1939ad2b219c8d6
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
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