Searched hist:be87d920bfd8c70dc3c96dc726f1686bd3430cc0 (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/plat/nvidia/tegra/include/drivers/ |
| H A D | memctrl_v2.h | be87d920bfd8c70dc3c96dc726f1686bd3430cc0 Wed Feb 17 23:07:49 UTC 2016 Varun Wadekar <vwadekar@nvidia.com> Tegra: memctrl_v2: implement MC txn override WAR
This patch sets the Memory Controller's TXN_OVERRIDE registers
for most write clients to CGID_ADR. This ensures ordering is maintained.
In some cases WAW ordering problems could occur. There are different
settings for Tegra version A01 v A02.
Original changes by Alex Waterman <alexw@nvidia.com>
Change-Id: I82ea02afa43a24250ed56985757b83e78e71178c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| /rk3399_ARM-atf/plat/nvidia/tegra/include/t186/ |
| H A D | tegra_def.h | be87d920bfd8c70dc3c96dc726f1686bd3430cc0 Wed Feb 17 23:07:49 UTC 2016 Varun Wadekar <vwadekar@nvidia.com> Tegra: memctrl_v2: implement MC txn override WAR
This patch sets the Memory Controller's TXN_OVERRIDE registers
for most write clients to CGID_ADR. This ensures ordering is maintained.
In some cases WAW ordering problems could occur. There are different
settings for Tegra version A01 v A02.
Original changes by Alex Waterman <alexw@nvidia.com>
Change-Id: I82ea02afa43a24250ed56985757b83e78e71178c
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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