Searched hist:b5e01eecc89e3e5c2ed3c17b803529be3c3702fb (Results 1 – 5 of 5) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-am33xx/ |
| H A D | gpio.h | b5e01eecc89e3e5c2ed3c17b803529be3c3702fb Tue Dec 10 09:32:23 UTC 2013 Lokesh Vutla <lokeshvutla@ti.com> ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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| H A D | ddr_defs.h | b5e01eecc89e3e5c2ed3c17b803529be3c3702fb Tue Dec 10 09:32:23 UTC 2013 Lokesh Vutla <lokeshvutla@ti.com> ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
|
| /rk3399_rockchip-uboot/board/ti/am43xx/ |
| H A D | mux.c | b5e01eecc89e3e5c2ed3c17b803529be3c3702fb Tue Dec 10 09:32:23 UTC 2013 Lokesh Vutla <lokeshvutla@ti.com> ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
|
| H A D | board.c | b5e01eecc89e3e5c2ed3c17b803529be3c3702fb Tue Dec 10 09:32:23 UTC 2013 Lokesh Vutla <lokeshvutla@ti.com> ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
|
| /rk3399_rockchip-uboot/arch/arm/include/asm/ |
| H A D | emif.h | b5e01eecc89e3e5c2ed3c17b803529be3c3702fb Tue Dec 10 09:32:23 UTC 2013 Lokesh Vutla <lokeshvutla@ti.com> ARM: AM43xx: GP_EVM: Add support for DDR3
GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
|