xref: /rk3399_rockchip-uboot/arch/arm/include/asm/arch-am33xx/gpio.h (revision 4eaf126e0634d9797c00ed2650e2d1396a4a69a2)
13b97152bSSteve Sakoman /*
21a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
33b97152bSSteve Sakoman  */
43b97152bSSteve Sakoman #ifndef _GPIO_AM33xx_H
53b97152bSSteve Sakoman #define _GPIO_AM33xx_H
63b97152bSSteve Sakoman 
73b97152bSSteve Sakoman #include <asm/omap_gpio.h>
83b97152bSSteve Sakoman 
9*4eaf126eSNikita Kiryanov #ifdef CONFIG_AM43XX
10*4eaf126eSNikita Kiryanov #define OMAP_MAX_GPIO		192
11*4eaf126eSNikita Kiryanov #else
1287bd05d7SAxel Lin #define OMAP_MAX_GPIO		128
13*4eaf126eSNikita Kiryanov #endif
1487bd05d7SAxel Lin 
153b97152bSSteve Sakoman #define AM33XX_GPIO0_BASE       0x44E07000
163b97152bSSteve Sakoman #define AM33XX_GPIO1_BASE       0x4804C000
173b97152bSSteve Sakoman #define AM33XX_GPIO2_BASE       0x481AC000
183b97152bSSteve Sakoman #define AM33XX_GPIO3_BASE       0x481AE000
19cd8341b7SDave Gerlach #define AM33XX_GPIO4_BASE	0x48320000
20cd8341b7SDave Gerlach #define AM33XX_GPIO5_BASE	0x48322000
21b5e01eecSLokesh Vutla 
22b5e01eecSLokesh Vutla /* GPIO CTRL register */
23b5e01eecSLokesh Vutla #define GPIO_CTRL_DISABLEMODULE_SHIFT	0
24b5e01eecSLokesh Vutla #define GPIO_CTRL_DISABLEMODULE_MASK	(1 << 0)
25b5e01eecSLokesh Vutla #define GPIO_CTRL_ENABLEMODULE		GPIO_CTRL_DISABLEMODULE_MASK
26b5e01eecSLokesh Vutla 
27b5e01eecSLokesh Vutla /* GPIO OUTPUT ENABLE register */
28b5e01eecSLokesh Vutla #define GPIO_OE_ENABLE(x)		(1 << x)
29b5e01eecSLokesh Vutla 
30b5e01eecSLokesh Vutla /* GPIO SETDATAOUT register */
31b5e01eecSLokesh Vutla #define GPIO_SETDATAOUT(x)		(1 << x)
323b97152bSSteve Sakoman #endif /* _GPIO_AM33xx_H */
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