Searched hist:afc2ed63f9c83a3b7408d804cbe22f02d34d075d (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a710.h | afc2ed63f9c83a3b7408d804cbe22f02d34d075d Wed Mar 31 23:45:55 UTC 2021 Bipin Ravi <bipin.ravi@arm.com> errata: workaround for Cortex-A710 erratum 2017096
Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1[8] to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3
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| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a710.S | afc2ed63f9c83a3b7408d804cbe22f02d34d075d Wed Mar 31 23:45:55 UTC 2021 Bipin Ravi <bipin.ravi@arm.com> errata: workaround for Cortex-A710 erratum 2017096
Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1[8] to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | afc2ed63f9c83a3b7408d804cbe22f02d34d075d Wed Mar 31 23:45:55 UTC 2021 Bipin Ravi <bipin.ravi@arm.com> errata: workaround for Cortex-A710 erratum 2017096
Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1[8] to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | afc2ed63f9c83a3b7408d804cbe22f02d34d075d Wed Mar 31 23:45:55 UTC 2021 Bipin Ravi <bipin.ravi@arm.com> errata: workaround for Cortex-A710 erratum 2017096
Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1[8] to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3
|