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Searched hist:a8d81d61e120f2e5958f996cd59ab5219a8a3cce (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_system_manager.ha8d81d61e120f2e5958f996cd59ab5219a8a3cce Fri Oct 04 08:13:11 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): implement soc and lwsoc bridge control for burst speed

Implement burst speed read/write for SOC and LWSOC. Set bridge control
register to enable the register bit

Change-Id: I815b912cb90d79a548163d198eea177d70dfbc0d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
/rk3399_ARM-atf/plat/intel/soc/common/soc/
H A Dsocfpga_reset_manager.ca8d81d61e120f2e5958f996cd59ab5219a8a3cce Fri Oct 04 08:13:11 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): implement soc and lwsoc bridge control for burst speed

Implement burst speed read/write for SOC and LWSOC. Set bridge control
register to enable the register bit

Change-Id: I815b912cb90d79a548163d198eea177d70dfbc0d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>