Searched hist:a63332c517ac5699644d3e2fbf159d3e35c32549 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a78.h | a63332c517ac5699644d3e2fbf159d3e35c32549 Tue Feb 28 20:51:28 UTC 2023 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-A78 erratum 2742426
Cortex-A78 erratum 2742426 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.
The workaround is to set the CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1401784/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I42506a87d41c9e2b30bc78c08d22f36e1f9635c1
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a78.S | a63332c517ac5699644d3e2fbf159d3e35c32549 Tue Feb 28 20:51:28 UTC 2023 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-A78 erratum 2742426
Cortex-A78 erratum 2742426 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.
The workaround is to set the CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1401784/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I42506a87d41c9e2b30bc78c08d22f36e1f9635c1
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | a63332c517ac5699644d3e2fbf159d3e35c32549 Tue Feb 28 20:51:28 UTC 2023 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-A78 erratum 2742426
Cortex-A78 erratum 2742426 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.
The workaround is to set the CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1401784/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I42506a87d41c9e2b30bc78c08d22f36e1f9635c1
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | a63332c517ac5699644d3e2fbf159d3e35c32549 Tue Feb 28 20:51:28 UTC 2023 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-A78 erratum 2742426
Cortex-A78 erratum 2742426 is a Cat B erratum that applies to
all revisions <= r1p2 and is still open.
The workaround is to set the CPUACTLR5_EL1[56:55] to 2'b01.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1401784/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I42506a87d41c9e2b30bc78c08d22f36e1f9635c1
|