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/rk3399_ARM-atf/plat/intel/soc/stratix10/
H A Dplatform.mk9c8f3af50a227cb095a629c0877ff82111c801a9 Tue Dec 24 02:42:52 UTC 2019 Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> intel: Add bridge control for FPGA reconfig

This is to make sure that bridge access in disabled before doing full
FPGA reconfiguration and turn re-enable it once the configuration
succeed.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I1f42fbf04ac1625048bbdf21b8a0443464ed833d
/rk3399_ARM-atf/plat/intel/soc/agilex/
H A Dplatform.mk9c8f3af50a227cb095a629c0877ff82111c801a9 Tue Dec 24 02:42:52 UTC 2019 Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> intel: Add bridge control for FPGA reconfig

This is to make sure that bridge access in disabled before doing full
FPGA reconfiguration and turn re-enable it once the configuration
succeed.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I1f42fbf04ac1625048bbdf21b8a0443464ed833d
/rk3399_ARM-atf/plat/intel/soc/common/
H A Dsocfpga_sip_svc.c9c8f3af50a227cb095a629c0877ff82111c801a9 Tue Dec 24 02:42:52 UTC 2019 Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> intel: Add bridge control for FPGA reconfig

This is to make sure that bridge access in disabled before doing full
FPGA reconfiguration and turn re-enable it once the configuration
succeed.

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I1f42fbf04ac1625048bbdf21b8a0443464ed833d