Searched hist:"9 af07df0506af9a4230bafb3e74c769f0de3ec9a" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a55.h | 9af07df0506af9a4230bafb3e74c769f0de3ec9a Tue May 28 08:52:48 UTC 2019 Ambroise Vincent <ambroise.vincent@arm.com> Cortex-A55: workarounds for errata 1221012
The workaround is added to the Cortex-A55 cpu specific file. The
workaround is disabled by default and have to be explicitly enabled by
the platform integrator.
Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a55.S | 9af07df0506af9a4230bafb3e74c769f0de3ec9a Tue May 28 08:52:48 UTC 2019 Ambroise Vincent <ambroise.vincent@arm.com> Cortex-A55: workarounds for errata 1221012
The workaround is added to the Cortex-A55 cpu specific file. The
workaround is disabled by default and have to be explicitly enabled by
the platform integrator.
Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | 9af07df0506af9a4230bafb3e74c769f0de3ec9a Tue May 28 08:52:48 UTC 2019 Ambroise Vincent <ambroise.vincent@arm.com> Cortex-A55: workarounds for errata 1221012
The workaround is added to the Cortex-A55 cpu specific file. The
workaround is disabled by default and have to be explicitly enabled by
the platform integrator.
Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 9af07df0506af9a4230bafb3e74c769f0de3ec9a Tue May 28 08:52:48 UTC 2019 Ambroise Vincent <ambroise.vincent@arm.com> Cortex-A55: workarounds for errata 1221012
The workaround is added to the Cortex-A55 cpu specific file. The
workaround is disabled by default and have to be explicitly enabled by
the platform integrator.
Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
|