1d40ab484SDavid Wang /* 2*4c700c15SGovindraj Raja * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. 3d40ab484SDavid Wang * 4d40ab484SDavid Wang * SPDX-License-Identifier: BSD-3-Clause 5d40ab484SDavid Wang */ 6d40ab484SDavid Wang 7c3cf06f1SAntonio Nino Diaz #ifndef CORTEX_A55_H 8c3cf06f1SAntonio Nino Diaz #define CORTEX_A55_H 9d40ab484SDavid Wang 101a74e4a8SAntonio Nino Diaz #include <lib/utils_def.h> 111a74e4a8SAntonio Nino Diaz 12d40ab484SDavid Wang /* Cortex-A55 MIDR for revision 0 */ 131a74e4a8SAntonio Nino Diaz #define CORTEX_A55_MIDR U(0x410fd050) 14d40ab484SDavid Wang 15d40ab484SDavid Wang /******************************************************************************* 16d40ab484SDavid Wang * CPU Extended Control register specific definitions. 17d40ab484SDavid Wang ******************************************************************************/ 18d40ab484SDavid Wang #define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7 19d40ab484SDavid Wang #define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4 20d40ab484SDavid Wang 21a6cc6610SAmbroise Vincent #define CORTEX_A55_CPUECTLR_EL1_L1WSCTL (ULL(3) << 25) 22a6cc6610SAmbroise Vincent 231afeee92SAmbroise Vincent /******************************************************************************* 241afeee92SAmbroise Vincent * CPU Auxiliary Control register specific definitions. 251afeee92SAmbroise Vincent ******************************************************************************/ 261afeee92SAmbroise Vincent #define CORTEX_A55_CPUACTLR_EL1 S3_0_C15_C1_0 271afeee92SAmbroise Vincent 28a6cc6610SAmbroise Vincent #define CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING (ULL(1) << 24) 291afeee92SAmbroise Vincent #define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31) 306ab87d29SAmbroise Vincent #define CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS (ULL(1) << 49) 311afeee92SAmbroise Vincent 32a6cc6610SAmbroise Vincent /******************************************************************************* 33a6cc6610SAmbroise Vincent * CPU Identification register specific definitions. 34a6cc6610SAmbroise Vincent ******************************************************************************/ 35a6cc6610SAmbroise Vincent #define CORTEX_A55_CLIDR_EL1 S3_1_C0_C0_1 36a6cc6610SAmbroise Vincent 37a6cc6610SAmbroise Vincent #define CORTEX_A55_CLIDR_EL1_CTYPE3 (ULL(7) << 6) 38a6cc6610SAmbroise Vincent 39d40ab484SDavid Wang /* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */ 401a74e4a8SAntonio Nino Diaz #define CORTEX_A55_CORE_PWRDN_EN_MASK U(0x1) 41d40ab484SDavid Wang 429af07df0SAmbroise Vincent /* Instruction patching registers */ 439af07df0SAmbroise Vincent #define CPUPSELR_EL3 S3_6_C15_C8_0 449af07df0SAmbroise Vincent #define CPUPCR_EL3 S3_6_C15_C8_1 459af07df0SAmbroise Vincent #define CPUPOR_EL3 S3_6_C15_C8_2 469af07df0SAmbroise Vincent #define CPUPMR_EL3 S3_6_C15_C8_3 479af07df0SAmbroise Vincent 48c3cf06f1SAntonio Nino Diaz #endif /* CORTEX_A55_H */ 49