Searched hist:"939 f66d6c46a8fe8cac708ac8e52afea3ff7a095" (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/lib/el3_runtime/aarch32/ |
| H A D | context_mgmt.c | 939f66d6c46a8fe8cac708ac8e52afea3ff7a095 Fri Nov 25 00:21:59 UTC 2016 David Cunado <david.cunado@arm.com> Reset EL2 and EL3 configurable controls
This patch resets EL2 and EL3 registers that have architecturally
UNKNOWN values on reset and that also provide EL2/EL3 configuration
and trap controls.
Specifically, the EL2 physical timer is disabled to prevent timer
interrups into EL2 - CNTHP_CTL_EL2 and CNTHP_CTL for AArch64 and AArch32,
respectively.
Additionally, for AArch64, HSTR_EL2 is reset to avoid unexpected traps of
non-secure access to certain system registers at EL1 or lower.
For AArch32, the patch also reverts the reset to SDCR which was
incorrectly added in a previous change.
Change-Id: If00eaa23afa7dd36a922265194ccd6223187414f
Signed-off-by: David Cunado <david.cunado@arm.com>
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| /rk3399_ARM-atf/lib/el3_runtime/aarch64/ |
| H A D | context_mgmt.c | 939f66d6c46a8fe8cac708ac8e52afea3ff7a095 Fri Nov 25 00:21:59 UTC 2016 David Cunado <david.cunado@arm.com> Reset EL2 and EL3 configurable controls
This patch resets EL2 and EL3 registers that have architecturally
UNKNOWN values on reset and that also provide EL2/EL3 configuration
and trap controls.
Specifically, the EL2 physical timer is disabled to prevent timer
interrups into EL2 - CNTHP_CTL_EL2 and CNTHP_CTL for AArch64 and AArch32,
respectively.
Additionally, for AArch64, HSTR_EL2 is reset to avoid unexpected traps of
non-secure access to certain system registers at EL1 or lower.
For AArch32, the patch also reverts the reset to SDCR which was
incorrectly added in a previous change.
Change-Id: If00eaa23afa7dd36a922265194ccd6223187414f
Signed-off-by: David Cunado <david.cunado@arm.com>
|