Searched hist:"8 e9d8acca4f8141b72d2d32846317954124c17ec" (Results 1 – 2 of 2) sorted by relevance
| /optee_os/core/arch/arm/plat-vexpress/ |
| H A D | main.c | 8e9d8acca4f8141b72d2d32846317954124c17ec Tue Jan 09 18:48:10 UTC 2024 Jens Wiklander <jens.wiklander@linaro.org> plat-vexpress: configure CFG_CORE_ASYNC_NOTIF_GIC_INTID
When compiled for SPMC at S-EL1 (CFG_CORE_SEL1_SPMC=y), configure
CFG_CORE_ASYNC_NOTIF_GIC_INTID to an unused secure SGI that can be
donated to the normal world.
In boot_primary_init_intc(), only donate the interrupt id if it's in the
predefined secure SGI range.
Fixes: 462028ede02d ("qemu_armv8a: add GIC v3 redistributor base address")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| H A D | conf.mk | 8e9d8acca4f8141b72d2d32846317954124c17ec Tue Jan 09 18:48:10 UTC 2024 Jens Wiklander <jens.wiklander@linaro.org> plat-vexpress: configure CFG_CORE_ASYNC_NOTIF_GIC_INTID
When compiled for SPMC at S-EL1 (CFG_CORE_SEL1_SPMC=y), configure
CFG_CORE_ASYNC_NOTIF_GIC_INTID to an unused secure SGI that can be
donated to the normal world.
In boot_primary_init_intc(), only donate the interrupt id if it's in the
predefined secure SGI range.
Fixes: 462028ede02d ("qemu_armv8a: add GIC v3 redistributor base address")
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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