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/rk3399_ARM-atf/plat/socionext/synquacer/
H A Dsq_xlat_setup.c8cd37d7ba1988e7f86bd92ba75e388c3f04dc172 Fri Jun 15 09:40:16 UTC 2018 Sumit Garg <sumit.garg@linaro.org> synquacer: Enable MMU using xlat_tables_v2 library

BL31 runs from SRAM which is a non-coherent memory on synquacer. So
enable MMU with SRAM memory marked as Non-Cacheable and mark page tables
kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables
for Device address space.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
H A Dsq_bl31_setup.c8cd37d7ba1988e7f86bd92ba75e388c3f04dc172 Fri Jun 15 09:40:16 UTC 2018 Sumit Garg <sumit.garg@linaro.org> synquacer: Enable MMU using xlat_tables_v2 library

BL31 runs from SRAM which is a non-coherent memory on synquacer. So
enable MMU with SRAM memory marked as Non-Cacheable and mark page tables
kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables
for Device address space.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
/rk3399_ARM-atf/plat/socionext/synquacer/include/
H A Dsq_common.h8cd37d7ba1988e7f86bd92ba75e388c3f04dc172 Fri Jun 15 09:40:16 UTC 2018 Sumit Garg <sumit.garg@linaro.org> synquacer: Enable MMU using xlat_tables_v2 library

BL31 runs from SRAM which is a non-coherent memory on synquacer. So
enable MMU with SRAM memory marked as Non-Cacheable and mark page tables
kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables
for Device address space.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
H A Dplatform_def.h8cd37d7ba1988e7f86bd92ba75e388c3f04dc172 Fri Jun 15 09:40:16 UTC 2018 Sumit Garg <sumit.garg@linaro.org> synquacer: Enable MMU using xlat_tables_v2 library

BL31 runs from SRAM which is a non-coherent memory on synquacer. So
enable MMU with SRAM memory marked as Non-Cacheable and mark page tables
kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables
for Device address space.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>