Searched hist:"8 a855bd24329e081cf13a257c7d2dc3ab4e5dcca" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a710.h | 8a855bd24329e081cf13a257c7d2dc3ab4e5dcca Sun Feb 06 09:11:44 UTC 2022 Bipin Ravi <bipin.ravi@arm.com> fix(errata): workaround for Cortex-A710 erratum 2136059
Cortex-A710 erratum 2136059 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR5_EL1[44] to 1 which will cause
the CPP instruction to invalidate the hardware prefetcher state
trained from any EL.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I43a86a365418fb663cc1b6ab1d365b4beddae0bc
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| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a710.S | 8a855bd24329e081cf13a257c7d2dc3ab4e5dcca Sun Feb 06 09:11:44 UTC 2022 Bipin Ravi <bipin.ravi@arm.com> fix(errata): workaround for Cortex-A710 erratum 2136059
Cortex-A710 erratum 2136059 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR5_EL1[44] to 1 which will cause
the CPP instruction to invalidate the hardware prefetcher state
trained from any EL.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I43a86a365418fb663cc1b6ab1d365b4beddae0bc
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | 8a855bd24329e081cf13a257c7d2dc3ab4e5dcca Sun Feb 06 09:11:44 UTC 2022 Bipin Ravi <bipin.ravi@arm.com> fix(errata): workaround for Cortex-A710 erratum 2136059
Cortex-A710 erratum 2136059 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR5_EL1[44] to 1 which will cause
the CPP instruction to invalidate the hardware prefetcher state
trained from any EL.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I43a86a365418fb663cc1b6ab1d365b4beddae0bc
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 8a855bd24329e081cf13a257c7d2dc3ab4e5dcca Sun Feb 06 09:11:44 UTC 2022 Bipin Ravi <bipin.ravi@arm.com> fix(errata): workaround for Cortex-A710 erratum 2136059
Cortex-A710 erratum 2136059 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR5_EL1[44] to 1 which will cause
the CPP instruction to invalidate the hardware prefetcher state
trained from any EL.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I43a86a365418fb663cc1b6ab1d365b4beddae0bc
|