Searched hist:"8 a4f840b1e13b0187b373e014ea314c3dabb122d" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/drivers/nxp/clk/s32cc/include/ |
| H A D | s32cc-clk-regs.h | 8a4f840b1e13b0187b373e014ea314c3dabb122d Tue Sep 17 08:22:30 UTC 2024 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> feat(nxp-clk): enable the DDR clock
Enable the DDR clock by setting up its reset block, the associated
partition and configuring the clock tree above the MC_CGM mux.
Change-Id: Idfed24b3e74a189df87f9782886a91b906cd2022
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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| /rk3399_ARM-atf/drivers/nxp/clk/s32cc/ |
| H A D | s32cc_early_clks.c | 8a4f840b1e13b0187b373e014ea314c3dabb122d Tue Sep 17 08:22:30 UTC 2024 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> feat(nxp-clk): enable the DDR clock
Enable the DDR clock by setting up its reset block, the associated
partition and configuring the clock tree above the MC_CGM mux.
Change-Id: Idfed24b3e74a189df87f9782886a91b906cd2022
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
|
| H A D | s32cc_clk_drv.c | 8a4f840b1e13b0187b373e014ea314c3dabb122d Tue Sep 17 08:22:30 UTC 2024 Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com> feat(nxp-clk): enable the DDR clock
Enable the DDR clock by setting up its reset block, the associated
partition and configuring the clock tree above the MC_CGM mux.
Change-Id: Idfed24b3e74a189df87f9782886a91b906cd2022
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
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