Searched hist:"8853 eba6e1abbb7cd0d955adb37a0e5eefc0c73d" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/ti/k3low/include/ |
| H A D | platform_def.h | 8853eba6e1abbb7cd0d955adb37a0e5eefc0c73d Thu Jun 05 06:35:27 UTC 2025 Dhruva Gole <d-gole@ti.com> feat(ti): add mmu regions for am62l soc
Update the k3low bl31 platform setup to map required device regions
(USART, GIC, GTC, MMR, and mailbox) in the MMU. This ensures that all
necessary hardware blocks are accessible to the A53 cores on the
AM62L SoC.
Use 4K aligned address sizes wherever applicable, and update the
file header comment from "K3 SOC specific bl31_setup" to "k3low SoC
specific bl31_setup" to accurately represent the platform specific
nature of this file.
As part of the effort, rename WKUP_CTRL_MMR0_DEVICE_MANAGEMENT_BASE
to WKUP_CTRL_MMR0_BASE to make name shorter.
Change-Id: I58209bc9c780db3e452b09c2c939bb0c47a63ed1
Signed-off-by: Dhruva Gole <d-gole@ti.com>
|
| /rk3399_ARM-atf/plat/ti/k3low/board/am62lx/include/ |
| H A D | board_def.h | 8853eba6e1abbb7cd0d955adb37a0e5eefc0c73d Thu Jun 05 06:35:27 UTC 2025 Dhruva Gole <d-gole@ti.com> feat(ti): add mmu regions for am62l soc
Update the k3low bl31 platform setup to map required device regions
(USART, GIC, GTC, MMR, and mailbox) in the MMU. This ensures that all
necessary hardware blocks are accessible to the A53 cores on the
AM62L SoC.
Use 4K aligned address sizes wherever applicable, and update the
file header comment from "K3 SOC specific bl31_setup" to "k3low SoC
specific bl31_setup" to accurately represent the platform specific
nature of this file.
As part of the effort, rename WKUP_CTRL_MMR0_DEVICE_MANAGEMENT_BASE
to WKUP_CTRL_MMR0_BASE to make name shorter.
Change-Id: I58209bc9c780db3e452b09c2c939bb0c47a63ed1
Signed-off-by: Dhruva Gole <d-gole@ti.com>
|
| /rk3399_ARM-atf/plat/ti/k3low/common/ |
| H A D | am62l_psci.c | 8853eba6e1abbb7cd0d955adb37a0e5eefc0c73d Thu Jun 05 06:35:27 UTC 2025 Dhruva Gole <d-gole@ti.com> feat(ti): add mmu regions for am62l soc
Update the k3low bl31 platform setup to map required device regions
(USART, GIC, GTC, MMR, and mailbox) in the MMU. This ensures that all
necessary hardware blocks are accessible to the A53 cores on the
AM62L SoC.
Use 4K aligned address sizes wherever applicable, and update the
file header comment from "K3 SOC specific bl31_setup" to "k3low SoC
specific bl31_setup" to accurately represent the platform specific
nature of this file.
As part of the effort, rename WKUP_CTRL_MMR0_DEVICE_MANAGEMENT_BASE
to WKUP_CTRL_MMR0_BASE to make name shorter.
Change-Id: I58209bc9c780db3e452b09c2c939bb0c47a63ed1
Signed-off-by: Dhruva Gole <d-gole@ti.com>
|
| H A D | am62l_bl31_setup.c | 8853eba6e1abbb7cd0d955adb37a0e5eefc0c73d Thu Jun 05 06:35:27 UTC 2025 Dhruva Gole <d-gole@ti.com> feat(ti): add mmu regions for am62l soc
Update the k3low bl31 platform setup to map required device regions
(USART, GIC, GTC, MMR, and mailbox) in the MMU. This ensures that all
necessary hardware blocks are accessible to the A53 cores on the
AM62L SoC.
Use 4K aligned address sizes wherever applicable, and update the
file header comment from "K3 SOC specific bl31_setup" to "k3low SoC
specific bl31_setup" to accurately represent the platform specific
nature of this file.
As part of the effort, rename WKUP_CTRL_MMR0_DEVICE_MANAGEMENT_BASE
to WKUP_CTRL_MMR0_BASE to make name shorter.
Change-Id: I58209bc9c780db3e452b09c2c939bb0c47a63ed1
Signed-off-by: Dhruva Gole <d-gole@ti.com>
|