xref: /rk3399_ARM-atf/plat/ti/k3low/board/am62lx/include/board_def.h (revision 06bf26bc1f76265237df2303d78a8f475eab703d)
121b14fd2SDhruva Gole /*
221b14fd2SDhruva Gole  * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com
321b14fd2SDhruva Gole  *
421b14fd2SDhruva Gole  * SPDX-License-Identifier: BSD-3-Clause
521b14fd2SDhruva Gole  */
621b14fd2SDhruva Gole 
721b14fd2SDhruva Gole #ifndef BOARD_DEF_H
821b14fd2SDhruva Gole #define BOARD_DEF_H
921b14fd2SDhruva Gole 
1021b14fd2SDhruva Gole #include <lib/utils_def.h>
1121b14fd2SDhruva Gole 
1221b14fd2SDhruva Gole /* The ports must be in order and contiguous */
1321b14fd2SDhruva Gole #define K3_CLUSTER0_CORE_COUNT		U(2)
1421b14fd2SDhruva Gole #define K3_CLUSTER1_CORE_COUNT		U(0)
1521b14fd2SDhruva Gole #define K3_CLUSTER2_CORE_COUNT		U(0)
1621b14fd2SDhruva Gole #define K3_CLUSTER3_CORE_COUNT		U(0)
1721b14fd2SDhruva Gole 
1821b14fd2SDhruva Gole #define PLAT_PROC_START_ID		U(32)
1921b14fd2SDhruva Gole #define PLAT_PROC_DEVICE_START_ID	U(135)
2021b14fd2SDhruva Gole #define PLAT_CLUSTER_DEVICE_START_ID	U(134)
2121b14fd2SDhruva Gole #define PLAT_BOARD_DEVICE_ID		U(157)
2221b14fd2SDhruva Gole 
23*8853eba6SDhruva Gole #define MAILBOX_SHMEM_REGION_BASE	UL(0x70810000)
24*8853eba6SDhruva Gole #define MAILBOX_SHMEM_REGION_SIZE	UL(0x6000)
25*8853eba6SDhruva Gole 
2621b14fd2SDhruva Gole /* Pre-decided SRAM Addresses for sending and receiving messages */
2721b14fd2SDhruva Gole #define MAILBOX_TX_START_REGION		UL(0x70814000)
2821b14fd2SDhruva Gole #define MAILBOX_RX_START_REGION		UL(0x70815000)
2964e58ce3SDhruva Gole /* 1 slot in the memory buffer dedicated for IPC is 64 bytes */
3064e58ce3SDhruva Gole #define MAILBOX_RX_SLOT_SZ		U(64)
3164e58ce3SDhruva Gole /* There are 5 slots in the memory buffer dedicated for IPC */
3264e58ce3SDhruva Gole #define MAILBOX_RX_NUM_SLOTS		U(5)
3321b14fd2SDhruva Gole /*
3421b14fd2SDhruva Gole  * Pre-calculated MAX size of a message
3521b14fd2SDhruva Gole  * sec_hdr + (type/host/seq + flags) + payload
3621b14fd2SDhruva Gole  * 4 + 16 + 36
3721b14fd2SDhruva Gole  */
3821b14fd2SDhruva Gole #define MAILBOX_MAX_MESSAGE_SIZE	U(56)
3921b14fd2SDhruva Gole 
4064e58ce3SDhruva Gole /* Ensure the RX Slot size is not smaller than the max message size */
4164e58ce3SDhruva Gole #if (MAILBOX_MAX_MESSAGE_SIZE > MAILBOX_RX_SLOT_SZ)
4264e58ce3SDhruva Gole #error "MAILBOX_MAX_MESSAGE_SIZE > MAILBOX_RX_SLOT_SZ"
4364e58ce3SDhruva Gole #endif
4464e58ce3SDhruva Gole 
4521b14fd2SDhruva Gole #endif /* BOARD_DEF_H */
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