Searched hist:"8336 c94dc4c7b25d34bb6f3c5008720746407dad" (Results 1 – 5 of 5) sorted by relevance
| /rk3399_ARM-atf/plat/nvidia/tegra/include/t186/ |
| H A D | tegra186_private.h | 8336c94dc4c7b25d34bb6f3c5008720746407dad Thu Aug 09 22:11:23 UTC 2018 Varun Wadekar <vwadekar@nvidia.com> Tegra186: disable PROGRAMMABLE_RESET_ADDRESS
This patch disables the code to program reset vector for secondary
CPUs to a different entry point, than cold boot. The cold boot entry
point has the ability to differentiate between a cold boot and a warm
boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By
reusing the same entry point, we can lock the CPU reset vector during
cold boot.
Change-Id: Iad400841d57c139469e1d29b5d467197e11958c4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|
| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/ |
| H A D | plat_secondary.c | 8336c94dc4c7b25d34bb6f3c5008720746407dad Thu Aug 09 22:11:23 UTC 2018 Varun Wadekar <vwadekar@nvidia.com> Tegra186: disable PROGRAMMABLE_RESET_ADDRESS
This patch disables the code to program reset vector for secondary
CPUs to a different entry point, than cold boot. The cold boot entry
point has the ability to differentiate between a cold boot and a warm
boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By
reusing the same entry point, we can lock the CPU reset vector during
cold boot.
Change-Id: Iad400841d57c139469e1d29b5d467197e11958c4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|
| H A D | plat_trampoline.S | 8336c94dc4c7b25d34bb6f3c5008720746407dad Thu Aug 09 22:11:23 UTC 2018 Varun Wadekar <vwadekar@nvidia.com> Tegra186: disable PROGRAMMABLE_RESET_ADDRESS
This patch disables the code to program reset vector for secondary
CPUs to a different entry point, than cold boot. The cold boot entry
point has the ability to differentiate between a cold boot and a warm
boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By
reusing the same entry point, we can lock the CPU reset vector during
cold boot.
Change-Id: Iad400841d57c139469e1d29b5d467197e11958c4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|
| H A D | platform_t186.mk | 8336c94dc4c7b25d34bb6f3c5008720746407dad Thu Aug 09 22:11:23 UTC 2018 Varun Wadekar <vwadekar@nvidia.com> Tegra186: disable PROGRAMMABLE_RESET_ADDRESS
This patch disables the code to program reset vector for secondary
CPUs to a different entry point, than cold boot. The cold boot entry
point has the ability to differentiate between a cold boot and a warm
boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By
reusing the same entry point, we can lock the CPU reset vector during
cold boot.
Change-Id: Iad400841d57c139469e1d29b5d467197e11958c4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|
| H A D | plat_psci_handlers.c | 8336c94dc4c7b25d34bb6f3c5008720746407dad Thu Aug 09 22:11:23 UTC 2018 Varun Wadekar <vwadekar@nvidia.com> Tegra186: disable PROGRAMMABLE_RESET_ADDRESS
This patch disables the code to program reset vector for secondary
CPUs to a different entry point, than cold boot. The cold boot entry
point has the ability to differentiate between a cold boot and a warm
boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By
reusing the same entry point, we can lock the CPU reset vector during
cold boot.
Change-Id: Iad400841d57c139469e1d29b5d467197e11958c4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
|