168c7de6fSVarun Wadekar/* 25e2fe3a3SVarun Wadekar * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. 3a391d494SPritesh Raithatha * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 468c7de6fSVarun Wadekar * 582cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 668c7de6fSVarun Wadekar */ 768c7de6fSVarun Wadekar 868c7de6fSVarun Wadekar#include <arch.h> 968c7de6fSVarun Wadekar#include <asm_macros.S> 105e2fe3a3SVarun Wadekar#include <common/bl_common.h> 1168c7de6fSVarun Wadekar#include <memctrl_v2.h> 1209d40e0eSAntonio Nino Diaz#include <plat/common/common_def.h> 1368c7de6fSVarun Wadekar#include <tegra_def.h> 1468c7de6fSVarun Wadekar 15a391d494SPritesh Raithatha#define TEGRA186_MC_CTX_SIZE 0x93 1668c7de6fSVarun Wadekar 17*2139c9c8SVarun Wadekar .globl tegra186_get_mc_ctx_size 1868c7de6fSVarun Wadekar 1968c7de6fSVarun Wadekar /* 20*2139c9c8SVarun Wadekar * Tegra186 reset data (offset 0x0 - 0x420) 2168c7de6fSVarun Wadekar * 22*2139c9c8SVarun Wadekar * 0x000: MC context start 23*2139c9c8SVarun Wadekar * 0x420: MC context end 2468c7de6fSVarun Wadekar */ 2568c7de6fSVarun Wadekar 2668c7de6fSVarun Wadekar .align 4 27a391d494SPritesh Raithatha__tegra186_mc_context: 28a391d494SPritesh Raithatha .rept TEGRA186_MC_CTX_SIZE 2968c7de6fSVarun Wadekar .quad 0 3068c7de6fSVarun Wadekar .endr 3168c7de6fSVarun Wadekar 3268c7de6fSVarun Wadekar .align 4 33*2139c9c8SVarun Wadekar__tegra186_mc_context_end: 34889c07c7SVarun Wadekar 35a391d494SPritesh Raithatha/* return the size of the MC context */ 36*2139c9c8SVarun Wadekarfunc tegra186_get_mc_ctx_size 37*2139c9c8SVarun Wadekar adr x0, __tegra186_mc_context_end 38*2139c9c8SVarun Wadekar adr x1, __tegra186_mc_context 39889c07c7SVarun Wadekar sub x0, x0, x1 40889c07c7SVarun Wadekar ret 41*2139c9c8SVarun Wadekarendfunc tegra186_get_mc_ctx_size 42