Searched hist:"81 c2a044e2d8cb06c66c44300741d449b969fcf1" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/drivers/marvell/secure_dfx_access/ |
| H A D | misc_dfx.c | 81c2a044e2d8cb06c66c44300741d449b969fcf1 Fri Jan 03 08:35:21 UTC 2020 Grzegorz Jaszczyk <jaz@semihalf.com> drivers: marvell: add support for secure read/write of dfx register-set
Since the dfx register set is going to be marked as secure expose dfx
secure read and write function via SiP services. In introduced misc_dfx
driver some registers are white-listed so non-secure software can still
access them.
This will allow non-secure word drivers access some white-listed
registers related to e.g.: Sample at reset, efuses, SoC type and
revision ID accesses.
Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25055
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
|
| H A D | dfx.h | 81c2a044e2d8cb06c66c44300741d449b969fcf1 Fri Jan 03 08:35:21 UTC 2020 Grzegorz Jaszczyk <jaz@semihalf.com> drivers: marvell: add support for secure read/write of dfx register-set
Since the dfx register set is going to be marked as secure expose dfx
secure read and write function via SiP services. In introduced misc_dfx
driver some registers are white-listed so non-secure software can still
access them.
This will allow non-secure word drivers access some white-listed
registers related to e.g.: Sample at reset, efuses, SoC type and
revision ID accesses.
Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25055
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
|
| /rk3399_ARM-atf/plat/marvell/armada/common/ |
| H A D | mrvl_sip_svc.c | 81c2a044e2d8cb06c66c44300741d449b969fcf1 Fri Jan 03 08:35:21 UTC 2020 Grzegorz Jaszczyk <jaz@semihalf.com> drivers: marvell: add support for secure read/write of dfx register-set
Since the dfx register set is going to be marked as secure expose dfx
secure read and write function via SiP services. In introduced misc_dfx
driver some registers are white-listed so non-secure software can still
access them.
This will allow non-secure word drivers access some white-listed
registers related to e.g.: Sample at reset, efuses, SoC type and
revision ID accesses.
Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25055
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
|
| /rk3399_ARM-atf/plat/marvell/armada/a8k/common/ |
| H A D | a8k_common.mk | 81c2a044e2d8cb06c66c44300741d449b969fcf1 Fri Jan 03 08:35:21 UTC 2020 Grzegorz Jaszczyk <jaz@semihalf.com> drivers: marvell: add support for secure read/write of dfx register-set
Since the dfx register set is going to be marked as secure expose dfx
secure read and write function via SiP services. In introduced misc_dfx
driver some registers are white-listed so non-secure software can still
access them.
This will allow non-secure word drivers access some white-listed
registers related to e.g.: Sample at reset, efuses, SoC type and
revision ID accesses.
Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25055
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
|