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2939f68a |
| 20-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I8f3afbe3,I441e7c69,I2e9465f7,Ib8756cd3,Iebe6ea7c, ... into integration
* changes: plat/marvell: remove subversion from Marvell make files drivers/marvell: check if TRNG unit is pr
Merge changes I8f3afbe3,I441e7c69,I2e9465f7,Ib8756cd3,Iebe6ea7c, ... into integration
* changes: plat/marvell: remove subversion from Marvell make files drivers/marvell: check if TRNG unit is present plat/marvell: a8k: move efuse definitions to separate header plat/marvell/armada: fix TRNG return SMC handling drivers: marvell: comphy: add rx training on 10G port plat/marvell/armada: postpone MSS CPU startup to BL31 stage plat: marvell: armada: a8k: Fix LD selector mask plat/marvell/armada: allow builds without MSS support drivers: marvell: misc-dfx: extend dfx whitelist drivers: marvell: add support for secure read/write of dfx register-set ddr_phy: use smc calls to access ddr phy registers drivers: marvell: thermal: use dedicated function for thermal SiPs drivers: marvell: add thermal sensor driver and expose it via SIP service fix: plat: marvell: fix MSS loader for A8K family
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| #
81c2a044 |
| 03-Jan-2020 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: add support for secure read/write of dfx register-set
Since the dfx register set is going to be marked as secure expose dfx secure read and write function via SiP services. In intr
drivers: marvell: add support for secure read/write of dfx register-set
Since the dfx register set is going to be marked as secure expose dfx secure read and write function via SiP services. In introduced misc_dfx driver some registers are white-listed so non-secure software can still access them.
This will allow non-secure word drivers access some white-listed registers related to e.g.: Sample at reset, efuses, SoC type and revision ID accesses.
Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/25055 Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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| #
0cedca63 |
| 02-Jan-2020 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: thermal: use dedicated function for thermal SiPs
Since more drivers which uses dfx register set need to be handled with use of SiP services, use dedicated and more meaningful name
drivers: marvell: thermal: use dedicated function for thermal SiPs
Since more drivers which uses dfx register set need to be handled with use of SiP services, use dedicated and more meaningful name for thermal SiP services.
Change-Id: Ic2ac27535a4902477df8edc4c86df3e34cb2344f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/25054 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
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| #
ad416958 |
| 18-Dec-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
drivers: marvell: add thermal sensor driver and expose it via SIP service
Since the dfx register set is going to be marked as secure (in order to protect efuse registers for non secure access), acce
drivers: marvell: add thermal sensor driver and expose it via SIP service
Since the dfx register set is going to be marked as secure (in order to protect efuse registers for non secure access), accessing thermal registers which are part of dfx register set, will not be possible from lower exception levels. Due to above expose thermal driver as a SiP service. This will allow Linux and U-Boot thermal driver to initialise and perform various operations on thermal sensor.
The thermal sensor driver is based on Linux drivers/thermal/armada_thermal.c.
Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/20581 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
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