Searched hist:"7 d947650dc41712cfc8830068a7ce06d56c6c205" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | neoverse_v2.h | 7d947650dc41712cfc8830068a7ce06d56c6c205 Thu Aug 28 18:52:15 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> fix(cpus): workaround for Neoverse-V2 erratum 3841324
Neoverse-V2 erratum 3841324 is a Cat B erratum that applies to
r0p0 and r0p1. It is fixed in r0p2.
This erratum can be avoided by setting CPUACTLR_EL1[1]
prior to enabling MMU. This bit will disable a branch predictor
power savings feature. Disabling this power feature
results in negligible power movement and no performance impact.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I9b3a5266103e5000d207c7a270c65455d0646102
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | neoverse_v2.S | 7d947650dc41712cfc8830068a7ce06d56c6c205 Thu Aug 28 18:52:15 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> fix(cpus): workaround for Neoverse-V2 erratum 3841324
Neoverse-V2 erratum 3841324 is a Cat B erratum that applies to
r0p0 and r0p1. It is fixed in r0p2.
This erratum can be avoided by setting CPUACTLR_EL1[1]
prior to enabling MMU. This bit will disable a branch predictor
power savings feature. Disabling this power feature
results in negligible power movement and no performance impact.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I9b3a5266103e5000d207c7a270c65455d0646102
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | 7d947650dc41712cfc8830068a7ce06d56c6c205 Thu Aug 28 18:52:15 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> fix(cpus): workaround for Neoverse-V2 erratum 3841324
Neoverse-V2 erratum 3841324 is a Cat B erratum that applies to
r0p0 and r0p1. It is fixed in r0p2.
This erratum can be avoided by setting CPUACTLR_EL1[1]
prior to enabling MMU. This bit will disable a branch predictor
power savings feature. Disabling this power feature
results in negligible power movement and no performance impact.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I9b3a5266103e5000d207c7a270c65455d0646102
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 7d947650dc41712cfc8830068a7ce06d56c6c205 Thu Aug 28 18:52:15 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> fix(cpus): workaround for Neoverse-V2 erratum 3841324
Neoverse-V2 erratum 3841324 is a Cat B erratum that applies to
r0p0 and r0p1. It is fixed in r0p2.
This erratum can be avoided by setting CPUACTLR_EL1[1]
prior to enabling MMU. This bit will disable a branch predictor
power savings feature. Disabling this power feature
results in negligible power movement and no performance impact.
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2332927/latest
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I9b3a5266103e5000d207c7a270c65455d0646102
|