Searched hist:"744 bdbf732ffd2abf84b2431624051e93bc29f7b" (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cortex_a710.h | 744bdbf732ffd2abf84b2431624051e93bc29f7b Wed Sep 22 19:35:03 UTC 2021 nayanpatel-arm <nayankumar.patel@arm.com> fix(errata): workaround for Cortex-A710 erratum 2058056
Cortex-A710 erratum 2058056 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r2p0. It is still open. The workaround
is to write the value 4'b1001 to the PF_MODE bits in the
IMP_CPUECTLR2_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I7ce5181b3b469fbbb16501e633116e119b8bf4f1
|
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a710.S | 744bdbf732ffd2abf84b2431624051e93bc29f7b Wed Sep 22 19:35:03 UTC 2021 nayanpatel-arm <nayankumar.patel@arm.com> fix(errata): workaround for Cortex-A710 erratum 2058056
Cortex-A710 erratum 2058056 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r2p0. It is still open. The workaround
is to write the value 4'b1001 to the PF_MODE bits in the
IMP_CPUECTLR2_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I7ce5181b3b469fbbb16501e633116e119b8bf4f1
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | 744bdbf732ffd2abf84b2431624051e93bc29f7b Wed Sep 22 19:35:03 UTC 2021 nayanpatel-arm <nayankumar.patel@arm.com> fix(errata): workaround for Cortex-A710 erratum 2058056
Cortex-A710 erratum 2058056 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r2p0. It is still open. The workaround
is to write the value 4'b1001 to the PF_MODE bits in the
IMP_CPUECTLR2_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I7ce5181b3b469fbbb16501e633116e119b8bf4f1
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | 744bdbf732ffd2abf84b2431624051e93bc29f7b Wed Sep 22 19:35:03 UTC 2021 nayanpatel-arm <nayankumar.patel@arm.com> fix(errata): workaround for Cortex-A710 erratum 2058056
Cortex-A710 erratum 2058056 is a Cat B erratum that applies to
revisions r0p0, r1p0, and r2p0. It is still open. The workaround
is to write the value 4'b1001 to the PF_MODE bits in the
IMP_CPUECTLR2_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I7ce5181b3b469fbbb16501e633116e119b8bf4f1
|