Searched hist:"728 b393f3b012ac46505151b80af1d4334786845" (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/arch/x86/dts/ |
| H A D | galileo.dts | 728b393f3b012ac46505151b80af1d4334786845 Wed Feb 04 08:26:12 UTC 2015 Bin Meng <bmeng.cn@gmail.com> x86: Add SPI support to quark/galileo
The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
|
| /rk3399_rockchip-uboot/arch/x86/cpu/quark/ |
| H A D | quark.c | 728b393f3b012ac46505151b80af1d4334786845 Wed Feb 04 08:26:12 UTC 2015 Bin Meng <bmeng.cn@gmail.com> x86: Add SPI support to quark/galileo
The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
|
| /rk3399_rockchip-uboot/drivers/spi/ |
| H A D | ich.c | 728b393f3b012ac46505151b80af1d4334786845 Wed Feb 04 08:26:12 UTC 2015 Bin Meng <bmeng.cn@gmail.com> x86: Add SPI support to quark/galileo
The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
|